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Hello everybody,

Please tell me the diffrence between the data types of verilog (wire
and register) and that of VHDL (signal and variabe).
Is wire the verilog equvalent of signal and the register the verilog
equvalent of variable.

(mohammed rafi) wrote in message news:<. com>...
> Hello everybody,
>
> Please tell me the diffrence between the data types of verilog (wire
> and register) and that of VHDL (signal and variabe).
> Is wire the verilog equvalent of signal and the register the verilog
> equvalent of variable.

In Verilog, a wire is a resolved signal that may have multiple
drivers, or sources. An output port is a wire. A wire cannot be driven
from a an always block.
A "reg" is like a variable in VHDL in that there is no resolotion
function, and can be assigned from multiple always blocks, with the
last assignment from any always block defining the value of this reg
object. However, a reg is also like a signal since it maintains timing
information for scheduling (blocking/nonblocking stuff) and you can
assign to an output port from an always block. The output has the
driver. In synthesis, it is not a good style to assign to a reg
object from multiple always blocks (you need to restrict the
assignment from one always block).

For wires, use the "assign" statement.
-----------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition,
2004 isbn 0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
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