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Thanks,

That depends on who you talk to, and how the numbers are calculated.
In general, it is good to be multi-langual.
I heard of figures like 60% Verilog in the US, but Europe is
highly embedded into VHDL (80 to 90%).
Those numbers are always disputed, and it would be interesting to see
the impact of SystemVerilog and VHDL200x, as those two upgrades bring some very
nice features to the HDLs in the area of assertions, verification, interface
defintions, better support of random numbers and other packages.
Ben
-----------------------------------------------------------------------------
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
0-9705394-6-0
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

VhdlCohen wrote:
> That depends on who you talk to, and how the numbers are calculated.
> In general, it is good to be multi-langual.
> I heard of figures like 60% Verilog in the US,

You also have to consider the market segment as
in the US FPGA and Defense market, VHDL rules

--
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Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

> but Europe is
> highly embedded into VHDL (80 to 90%).
> Those numbers are always disputed, and it would be interesting to see
> the impact of SystemVerilog and VHDL200x, as those two upgrades bring some very
> nice features to the HDLs in the area of assertions, verification, interface
> defintions, better support of random numbers and other packages.
> Ben
> -----------------------------------------------------------------------------
> Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
> http://www.vhdlcohen.com/
> Author of following textbooks:
> * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
> 0-9705394-6-0
> * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
> 0-9705394-2-8
> * Component Design by Example ", 2001 isbn 0-9705394-0-1
> * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
> * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
> ------------------------------------------------------------------------------