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How to drive record fields from procedure AND testbench?

 
 
Tom Hawkins
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Posts: n/a
 
      05-07-2004
http://www.velocityreviews.com/forums/(E-Mail Removed) (Peter Sommerfeld) wrote in message news:<(E-Mail Removed) m>...
> Hi Jim,
>
> Yes I would love to participate in the VHDL-200X effort. It's nice to
> see it's open to the non-members. Is there a target release date for
> VHDL-200X?
>
> This problem of the fields of a record appearing to be resolved as a
> group, and not individually, is particularly vexing to me. Hopefully I
> won't have to deal with it in the next VHDL version.
>
> -- Pete


Pete, I'm sure you're aware that Confluence does not have this
limitation:

component some_comp *gaggle with local_source external_reference is
gaggle.from_here <- local_source
gaggle.from_somewhere_else -> external_reference
end

And in the second thread that Mike referenced, the author mentioned
partial function applications. As a functional programming language,
Confluence has a few forms of partial functions:

system = {my_component _ _ _}

This allows you to instantiate a component with the ports unconnected,
then pass around the resulting system to be wired up later.

-Tom


> > >> gaggle.DSPaddr <= DSPaddr;
> > >> gaggle.DSPdata_in <= DSPdata;
> > >>-- . . . (rest of INs go here)
> > >>-- then OUTs:
> > >> nDHOLD <= gaggle.nDRDY;
> > >> nDRDY <= gaggle.nDRDY;
> > >> DSPdata <= gaggle.DSPdata_out when output_enabled
> > >> else (DSPdata'range => 'Z');


>
>
> > Peter,
> > As a PS to my other post, to date I have found
> > that if I want to work with a single record,
> > I have been limited to std_logic family.
> >
> > I have tried tinkering with integers and resolution
> > functions, but have had problems with resolving a value
> > to drive when the record field is not to be driven.
> > It seems that the resolution function is called at the
> > block level and there currently no way I could find to
> > work around this.
> >
> > This is a topic we are kicking around in the VHDL-200X
> > effort. I had wished for it to be part of the fast track
> > effort and I made a proposal, but it is not clear even to
> > me that the proposal is the best long term solution, so I
> > don't want to push it. My preference is to see what comes
> > up when we give more time and consideration to the problem.
> >
> > For more on the vhdl-200x effort, see:
> > http://www.eda.org/vhdl-200x
> >
> > IEEE standards are open to public participation.
> >
> > Best Regards,
> > Jim
> >
> >
> > > Hi Mike,
> > >
> > > Yes I found my problem, and it was unfortunately in a part of my
> > > record that I didn't post. In my record, I had a field that was of the
> > > physical type time which I was using inside my procedures for certain
> > > delays. ie:
> > >
> > > type rec is record
> > > ...
> > > clock_period : time;
> > > ...
> > > end record;
> > >
> > > So while I was assuming a signal-driving issue to be the problem, it
> > > was this field (which is still bizarre, because I set this field only
> > > once and never write it again, therefore, I would have thought, it
> > > could not be a problem). Anyways, I replaced this field with a clock
> > > signal which makes more sense now anyways and everything works great,
> > > and thanks to yours and Jim's replies, I understand what's going on
> > > much better too. I had better post the whole thing the next time I
> > > have a problem like this.
> > >
> > > -- Pete
> > >
> > >
> > >>Peter Sommerfeld wrote:
> > >>
> > >>
> > >>>Thanks for the reply. I must be on the right track, because it looks
> > >>>like I have been doing what you suggested in
> > >>>http://groups.google.com/groups?q=gaggle.DSPaddr. However, the InitBus
> > >>>call causes compile errors in my design.
> > >>
> > >>You have stumbled onto the procedure scope problem.
> > >>Re-read that thread and see the lines I added
> > >>to my example architecture below.
> > >>
> > >> -- Mike Treseler
> > >>
> > >>
> > >>------------------------------------------------------------
> > >>architecture synth of signal_structure is
> > >> -- note, I changed your type to data in and out signals
> > >>
> > >> type DSPIF_type is
> > >> record
> > >> DSPaddr : std_logic_vector(23 downto 0);
> > >> DSPdata_in : std_logic_vector(31 downto 0);
> > >> DSPdata_out : std_logic_vector(31 downto 0);
> > >> nDHOLD : std_logic;
> > >> nDHOLDA : std_logic;
> > >> nDPAGE : std_logic_vector(3 downto 0);
> > >> nDSTRB : std_logic;
> > >> nDBE : std_logic_vector(3 downto 0);
> > >> nDOE : std_logic;
> > >> nDWE : std_logic;
> > >> nDRDY : std_logic;
> > >> end record;
> > >>
> > >> signal gaggle : DSPIF_type;
> > >> signal output_enabled : boolean;
> > >>-------------------------------------------------------------------------------
> > >> -- Added proc example in scope
> > >> procedure InitBus( signal gaggle: inout DSPIF_type )
> > >> is begin end InitBus;
> > >>-------------------------------------------------------------------------------
> > >>begin
> > >> -- wire up signal structure to pins
> > >> gaggle.DSPaddr <= DSPaddr;
> > >> gaggle.DSPdata_in <= DSPdata;
> > >>-- . . . (rest of INs go here)
> > >>-- then OUTs:
> > >> nDHOLD <= gaggle.nDRDY;
> > >> nDRDY <= gaggle.nDRDY;
> > >> DSPdata <= gaggle.DSPdata_out when output_enabled
> > >> else (DSPdata'range => 'Z');
> > >>
> > >>-- processes using the gaggle signals go here
> > >>
> > >>end architecture synth;
> > >>
> > >>
> > >> -- Mike Treseler

> >
> >
> > --
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
> > Jim Lewis
> > Director of Training (E-Mail Removed)
> > SynthWorks Design Inc. http://www.SynthWorks.com
> > 1-503-590-4787
> >
> > Expert VHDL Training for Hardware Design and Verification
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

 
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Peter Sommerfeld
Guest
Posts: n/a
 
      05-09-2004
Hi Tom,

Yes I was, I think, a very early adopter of Confluence. I find the
language very impressive. Your FFT core on OpenCores is what got me
interested in it.

The biggest problem has been convincing my company to consider the
tool, which I have so far been unsuccessful with. As is typical, a
company adopts certain standards and practices, and the intertia is
difficult to overcome. Hopefully someday ...

Not that I'm unhappy with VHDL, in fact as long as I can work with the
latest FPGAs with whatever language I think I'll be very happy, but
from my tests I can write IP faster in Confluence than VHDL, and the
learning curve is shorter.

-- Pete

> Pete, I'm sure you're aware that Confluence does not have this
> limitation:
>
> component some_comp *gaggle with local_source external_reference is
> gaggle.from_here <- local_source
> gaggle.from_somewhere_else -> external_reference
> end
>
> And in the second thread that Mike referenced, the author mentioned
> partial function applications. As a functional programming language,
> Confluence has a few forms of partial functions:
>
> system = {my_component _ _ _}
>
> This allows you to instantiate a component with the ports unconnected,
> then pass around the resulting system to be wired up later.
>
> -Tom
>
>
> > > >> gaggle.DSPaddr <= DSPaddr;
> > > >> gaggle.DSPdata_in <= DSPdata;
> > > >>-- . . . (rest of INs go here)
> > > >>-- then OUTs:
> > > >> nDHOLD <= gaggle.nDRDY;
> > > >> nDRDY <= gaggle.nDRDY;
> > > >> DSPdata <= gaggle.DSPdata_out when output_enabled
> > > >> else (DSPdata'range => 'Z');

>
> >
> >
> > > Peter,
> > > As a PS to my other post, to date I have found
> > > that if I want to work with a single record,
> > > I have been limited to std_logic family.
> > >
> > > I have tried tinkering with integers and resolution
> > > functions, but have had problems with resolving a value
> > > to drive when the record field is not to be driven.
> > > It seems that the resolution function is called at the
> > > block level and there currently no way I could find to
> > > work around this.
> > >
> > > This is a topic we are kicking around in the VHDL-200X
> > > effort. I had wished for it to be part of the fast track
> > > effort and I made a proposal, but it is not clear even to
> > > me that the proposal is the best long term solution, so I
> > > don't want to push it. My preference is to see what comes
> > > up when we give more time and consideration to the problem.
> > >
> > > For more on the vhdl-200x effort, see:
> > > http://www.eda.org/vhdl-200x
> > >
> > > IEEE standards are open to public participation.
> > >
> > > Best Regards,
> > > Jim
> > >
> > >
> > > > Hi Mike,
> > > >
> > > > Yes I found my problem, and it was unfortunately in a part of my
> > > > record that I didn't post. In my record, I had a field that was of the
> > > > physical type time which I was using inside my procedures for certain
> > > > delays. ie:
> > > >
> > > > type rec is record
> > > > ...
> > > > clock_period : time;
> > > > ...
> > > > end record;
> > > >
> > > > So while I was assuming a signal-driving issue to be the problem, it
> > > > was this field (which is still bizarre, because I set this field only
> > > > once and never write it again, therefore, I would have thought, it
> > > > could not be a problem). Anyways, I replaced this field with a clock
> > > > signal which makes more sense now anyways and everything works great,
> > > > and thanks to yours and Jim's replies, I understand what's going on
> > > > much better too. I had better post the whole thing the next time I
> > > > have a problem like this.
> > > >
> > > > -- Pete
> > > >
> > > >
> > > >>Peter Sommerfeld wrote:
> > > >>
> > > >>
> > > >>>Thanks for the reply. I must be on the right track, because it looks
> > > >>>like I have been doing what you suggested in
> > > >>>http://groups.google.com/groups?q=gaggle.DSPaddr. However, the InitBus
> > > >>>call causes compile errors in my design.
> > > >>
> > > >>You have stumbled onto the procedure scope problem.
> > > >>Re-read that thread and see the lines I added
> > > >>to my example architecture below.
> > > >>
> > > >> -- Mike Treseler
> > > >>
> > > >>
> > > >>------------------------------------------------------------
> > > >>architecture synth of signal_structure is
> > > >> -- note, I changed your type to data in and out signals
> > > >>
> > > >> type DSPIF_type is
> > > >> record
> > > >> DSPaddr : std_logic_vector(23 downto 0);
> > > >> DSPdata_in : std_logic_vector(31 downto 0);
> > > >> DSPdata_out : std_logic_vector(31 downto 0);
> > > >> nDHOLD : std_logic;
> > > >> nDHOLDA : std_logic;
> > > >> nDPAGE : std_logic_vector(3 downto 0);
> > > >> nDSTRB : std_logic;
> > > >> nDBE : std_logic_vector(3 downto 0);
> > > >> nDOE : std_logic;
> > > >> nDWE : std_logic;
> > > >> nDRDY : std_logic;
> > > >> end record;
> > > >>
> > > >> signal gaggle : DSPIF_type;
> > > >> signal output_enabled : boolean;
> > > >>-------------------------------------------------------------------------------
> > > >> -- Added proc example in scope
> > > >> procedure InitBus( signal gaggle: inout DSPIF_type )
> > > >> is begin end InitBus;
> > > >>-------------------------------------------------------------------------------
> > > >>begin
> > > >> -- wire up signal structure to pins
> > > >> gaggle.DSPaddr <= DSPaddr;
> > > >> gaggle.DSPdata_in <= DSPdata;
> > > >>-- . . . (rest of INs go here)
> > > >>-- then OUTs:
> > > >> nDHOLD <= gaggle.nDRDY;
> > > >> nDRDY <= gaggle.nDRDY;
> > > >> DSPdata <= gaggle.DSPdata_out when output_enabled
> > > >> else (DSPdata'range => 'Z');
> > > >>
> > > >>-- processes using the gaggle signals go here
> > > >>
> > > >>end architecture synth;
> > > >>
> > > >>
> > > >> -- Mike Treseler
> > >
> > >
> > > --
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
> > > Jim Lewis
> > > Director of Training (E-Mail Removed)
> > > SynthWorks Design Inc. http://www.SynthWorks.com
> > > 1-503-590-4787
> > >
> > > Expert VHDL Training for Hardware Design and Verification
> > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

 
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