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Unconnected subelements of Composite Formal Ports

 
 
Nitin Khurana
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      04-27-2004
Hi,
I have a small doubt here, LRM section 1.1.1.2 states that "It is
an error if some of the subelements of a composite formal port are
connected and others are either unconnected or unassociated", Is this
true for input and output ports both? Because in general ouput ports can
be left unconnected but input ports can't be? So why can't some of the
subelements of a composite output port be connected and the rest of the
subelements be unconnected??

Would appreciate if some one can clarify this for me.

Thanks & Regards,
Nitin.

 
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Egbert Molenkamp
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      04-27-2004
An (output) port is unconnected if the keyword OPEN is used.
PORT MAP (...,OPEN,...)

For an input port an explicit initial value is required in case you want to
leave it unconnected.

Egbert Molenkamp

"Nitin Khurana" <(E-Mail Removed)> schreef in bericht
news:(E-Mail Removed)...
> Hi,
> I have a small doubt here, LRM section 1.1.1.2 states that "It is
> an error if some of the subelements of a composite formal port are
> connected and others are either unconnected or unassociated", Is this
> true for input and output ports both? Because in general ouput ports can
> be left unconnected but input ports can't be? So why can't some of the
> subelements of a composite output port be connected and the rest of the
> subelements be unconnected??
>
> Would appreciate if some one can clarify this for me.
>
> Thanks & Regards,
> Nitin.
>



 
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Jonathan Bromley
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      04-27-2004
On Tue, 27 Apr 2004 17:36:41 +0530, Nitin Khurana
<(E-Mail Removed)> wrote:

hi Nitin,

> [VHDL] LRM section 1.1.1.2 states that "It is
>an error if some of the subelements of a composite formal port are
>connected and others are either unconnected or unassociated", Is this
>true for input and output ports both?


Yes, I believe so. In fact, I think I made exactly this error in
a newsgroup posting a few days ago. Here are three instances of
a component with an 8-bit port:

component bvp is
port (a: out bit_vector(7 downto 0));
end component;

signal b,c: bit_vector(3 downto 0);
begin -- architecture
inst1: bvp port map (a => open);
inst2: bvp port map (a(3 downto 0) => b, a(7 downto 4) => c);
inst3: bvp port map (a(3 downto 0) => b, a(7 downto 4) => open);

inst1 is OK because it simply leaves the whole port open.
inst2 is OK because it connects two proper signals to different
fragments of the same port.
inst3 is wrong because of the LRM rule you mention.

> Because in general ouput ports can
>be left unconnected but input ports can't be?


No, that's not quite true. You can leave an input port floating,
if it has a default value.

> So why can't some of the
>subelements of a composite output port be connected and the rest of the
>subelements be unconnected??


I don't know, but I suspect it's closely related to the rather
severe rules about when it is or isn't possible to use "others =>".
I agree that it seems irksome, but in practice it's never been a
problem for me.
--
Jonathan Bromley, Consultant

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