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A<=0


A input 0


but

what is A=>0?

A output to 0???

Boki.

my_vector <= (others => '0'); -- all bit will be '0'
-- or
my_vector <= (A => '1', others => '0'); -- output(A) bit will be '1',
other bits will be '0'

So 'A' explain an index. 'A' is an interger (or positive, or natural, ...).

Laurent Gauch
www.amontec.com
--------------------------------------
WE HAVE ONLINE VHDL MEMO. IT IS FREE
--------------------------------------






Boki wrote:
> A<=0
>
>
> A input 0
>
>
> but
>
> what is A=>0?
>
> A output to 0???
>
> Boki.
>
>

Got it!!
Thank you very much!

Regards,
Boki


Amontec Team <> wrote in message news:<>...
> my_vector <= (others => '0'); -- all bit will be '0'
> -- or
> my_vector <= (A => '1', others => '0'); -- output(A) bit will be '1',
> other bits will be '0'
>
> So 'A' explain an index. 'A' is an interger (or positive, or natural, ...).
>
> Laurent Gauch
> www.amontec.com
> --------------------------------------
> WE HAVE ONLINE VHDL MEMO. IT IS FREE
> --------------------------------------
>
>
>
>
>
>
> Boki wrote:
> > A<=0
> >
> >
> > A input 0
> >
> >
> > but
> >
> > what is A=>0?
> >
> > A output to 0???
> >
> > Boki.
> >
> >