Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > why am i getting incompatible error

Reply
Thread Tools

why am i getting incompatible error

 
 
MNQ
Guest
Posts: n/a
 
      04-15-2004
Hi reader

I am trying to rotate a serial data stream in a 7 bit register but keep
getting the following error.
--------------------------------------------
Started process "Synthesize".
================================================== =======================
* HDL Compilation *
================================================== =======================
Compiling vhdl file H:/naveed/test/rotate.vhd in Library work.
ERROR:HDLParsers:800 - H:/naveed/test/rotate.vhd Line 35. Type of temp is
incompatible with type of data_in.
-->
Total memory usage is 40216 kilobytes
Error: XST failed
Reason:
Completed process "Synthesize".
-------------------------------------------

Can anyone tell me where I am going wrong. As I have spent along time and
cannot figure it out. I have pasted the code below. I would be grateful
for any hep.

Thanks
Naveed






--************************************************** ************************
*************
-- Project : Rotate register
-- Author : Naveed Qayyum
-- Date : 15th April 2004
-- Notes : Demonstration of the ror and rol function used to rotate the
serial data
-- received within the temp register.
--************************************************** ************************
*************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rotate is
Port ( clock : in std_logic;
reset : in std_logic;
data_in : in std_logic);
end rotate;

architecture Behavioral of rotate is

signal temp : bit_vector (7 downto 0);

begin

rotate : process (clock, reset)
begin
if reset='1' then
temp <= "00000000";
elsif clock='1' and clock'event then
temp(0) <= data_in;
temp <= temp rol 1;
end if;
end process rotate;

end Behavioral;




 
Reply With Quote
 
 
 
 
Ray Andraka
Guest
Posts: n/a
 
      04-15-2004
change
signal temp : bit_vector (7 downto 0);
to
signal temp : std_logic_vector (7 downto 0);

a bit vector is made up of type bit, which is not the same as type std_logic.


Also,
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

are non-standard libraries (compilation is not defined by a standard, so there
are differences from compiler to compiler).

Instead use:

use ieee.numeric_std.all;



MNQ wrote:

> Hi reader
>
> I am trying to rotate a serial data stream in a 7 bit register but keep
> getting the following error.
> --------------------------------------------
> Started process "Synthesize".
> ================================================== =======================
> * HDL Compilation *
> ================================================== =======================
> Compiling vhdl file H:/naveed/test/rotate.vhd in Library work.
> ERROR:HDLParsers:800 - H:/naveed/test/rotate.vhd Line 35. Type of temp is
> incompatible with type of data_in.
> -->
> Total memory usage is 40216 kilobytes
> Error: XST failed
> Reason:
> Completed process "Synthesize".
> -------------------------------------------
>
> Can anyone tell me where I am going wrong. As I have spent along time and
> cannot figure it out. I have pasted the code below. I would be grateful
> for any hep.
>
> Thanks
> Naveed
>
> --************************************************** ************************
> *************
> -- Project : Rotate register
> -- Author : Naveed Qayyum
> -- Date : 15th April 2004
> -- Notes : Demonstration of the ror and rol function used to rotate the
> serial data
> -- received within the temp register.
> --************************************************** ************************
> *************
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> -- Uncomment the following lines to use the declarations that are
> -- provided for instantiating Xilinx primitive components.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity rotate is
> Port ( clock : in std_logic;
> reset : in std_logic;
> data_in : in std_logic);
> end rotate;
>
> architecture Behavioral of rotate is
>
> signal temp : bit_vector (7 downto 0);
>
> begin
>
> rotate : process (clock, reset)
> begin
> if reset='1' then
> temp <= "00000000";
> elsif clock='1' and clock'event then
> temp(0) <= data_in;
> temp <= temp rol 1;
> end if;
> end process rotate;
>
> end Behavioral;


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email http://www.velocityreviews.com/forums/(E-Mail Removed)
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759


 
Reply With Quote
 
 
 
 
fe
Guest
Posts: n/a
 
      04-15-2004
> data_in : in std_logic);
> signal temp : bit_vector (7 downto 0);
> temp(0) <= data_in;
>


bit_vector is an array of bit

data_in : in std_logic);
signal temp : bit_vector (7 downto 0);
temp(0) <= to_bit(data_in);

or

data_in : in std_logic);
signal temp : std_logic_vector (7 downto 0);
temp(0) <= data_in;

or

data_in : in bit);
signal temp : bit_vector (7 downto 0);
temp(0) <= data_in;

regards
fe


 
Reply With Quote
 
deep
Guest
Posts: n/a
 
      04-16-2004
the compiler may not be supporting rol... you can do instead...
...
...
temp(0)<= data_in;
temp<= temp(6 downto 0) & temp(7);

...
...
hope this helps...

dk

 
Reply With Quote
 
deep
Guest
Posts: n/a
 
      04-16-2004
the compiler may not be supporting rol... you can do instead...
...
...
temp(0)<= data_in;
temp<= temp(6 downto 0) & temp(7);

...
...
hope this helps...

dk

 
Reply With Quote
 
MNQ
Guest
Posts: n/a
 
      04-16-2004
Hello everybody,

Thanks for all your help.

I dont think the ror or rol functions work in the xilinx's ISE 5.1.03i
version. I tried the method below and it worked for me.

I used the following method in the end to represent a 16 bit shift register.
Which is what I wanted in the end.

Thanks
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rotate is
Port ( clock : in std_logic;
reset : in std_logic;
data_in : in std_logic);
end rotate;

architecture Behavioral of rotate is

signal temp : std_logic_vector (15 downto 0);

begin

rotate : process (clock, reset, data_in)
begin
if reset='1' then
temp <= "0000000000000000";
elsif clock='1' and clock'event then
temp(15 downto 0) <= temp(14 downto 0) & data_in;
end if;
end process rotate;

end Behavioral;
--------------------------------------------------------------------------

Naveed

--
Mr Naveed Qayyum

www.mnq.org.uk
"MNQ" <(E-Mail Removed)> wrote in message
news:c5mea6$d0d$(E-Mail Removed)...
> Hi reader
>
> I am trying to rotate a serial data stream in a 7 bit register but keep
> getting the following error.
> --------------------------------------------
> Started process "Synthesize".
> ================================================== =======================
> * HDL Compilation *
> ================================================== =======================
> Compiling vhdl file H:/naveed/test/rotate.vhd in Library work.
> ERROR:HDLParsers:800 - H:/naveed/test/rotate.vhd Line 35. Type of temp is
> incompatible with type of data_in.
> -->
> Total memory usage is 40216 kilobytes
> Error: XST failed
> Reason:
> Completed process "Synthesize".
> -------------------------------------------
>
> Can anyone tell me where I am going wrong. As I have spent along time and
> cannot figure it out. I have pasted the code below. I would be grateful
> for any hep.
>
> Thanks
> Naveed
>
>
>
>
>
>
> --************************************************** **********************

**
> *************
> -- Project : Rotate register
> -- Author : Naveed Qayyum
> -- Date : 15th April 2004
> -- Notes : Demonstration of the ror and rol function used to rotate the
> serial data
> -- received within the temp register.
> --************************************************** **********************

**
> *************
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> -- Uncomment the following lines to use the declarations that are
> -- provided for instantiating Xilinx primitive components.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity rotate is
> Port ( clock : in std_logic;
> reset : in std_logic;
> data_in : in std_logic);
> end rotate;
>
> architecture Behavioral of rotate is
>
> signal temp : bit_vector (7 downto 0);
>
> begin
>
> rotate : process (clock, reset)
> begin
> if reset='1' then
> temp <= "00000000";
> elsif clock='1' and clock'event then
> temp(0) <= data_in;
> temp <= temp rol 1;
> end if;
> end process rotate;
>
> end Behavioral;
>
>
>
>



 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Why are Sphinx docs incompatible with Safari Reader? K.-Michael Aye Python 0 12-02-2011 03:27 PM
why not compile error on "incompatible interface cast"? gg9h0st Java 7 07-27-2008 09:15 AM
why arguments are not incompatible sumsin C++ 6 06-07-2008 02:22 PM
why why why why why Mr. SweatyFinger ASP .Net 4 12-21-2006 01:15 PM
findcontrol("PlaceHolderPrice") why why why why why why why why why why why Mr. SweatyFinger ASP .Net 2 12-02-2006 03:46 PM



Advertisments