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Hi,

in "Writing Testbenches" (Second Edition / Janick Bergeron) there is the following
VHDL construct : (page 161)



process
subtype byte is std_logic_vector(7 downto 0);
type region_typ is array(0 to 31) of byte;

type list_el_typ;
type list_el_ptr is access list_el_typ;
type list_el_typ is record
base_addr : natural;
region : region_typ;
next_region : list_el_ptr;
end record;
....

Some difficulties in understanding:

1.Why is "type list_el_typ" declared two times ?

2.What function does "access" have?

3.I cannot see what type "next_region" has. It has "list_el_ptr". But this type
is in turn described with access to the record type ?

I would appreciate some enlightenment.

Rgds
Andrés V.

VHDL allows to the use of dynamically create objects.
Probably the following link explains a lot to you:
http://mikro.e-technik.uni-ulm.de/vh...ml/node17.html

Egbert Molenkamp

"ALuPin" <> schreef in bericht
news: m...
> Hi,
>
> in "Writing Testbenches" (Second Edition / Janick Bergeron) there is the
following
> VHDL construct : (page 161)
>
>
>
> process
> subtype byte is std_logic_vector(7 downto 0);
> type region_typ is array(0 to 31) of byte;
>
> type list_el_typ;
> type list_el_ptr is access list_el_typ;
> type list_el_typ is record
> base_addr : natural;
> region : region_typ;
> next_region : list_el_ptr;
> end record;
> ...
>
> Some difficulties in understanding:
>
> 1.Why is "type list_el_typ" declared two times ?
>
> 2.What function does "access" have?
>
> 3.I cannot see what type "next_region" has. It has "list_el_ptr". But this
type
> is in turn described with access to the record type ?
>
> I would appreciate some enlightenment.
>
> Rgds
> Andrés V.

answering your questions directly:

1. type "list_el_typ" is declared twice to get around the
chicken-before-the-egg situation caused by one type referencing another
type. the technique illustrated in the example you posted is used for
creating linked data structures.

the statement "type list_el_typ;" is an incomplete type declaration. this
tells the compliler that the type will be completely defined in the
following code. in the mean time, references to the incomplete type may be
created. that's where "type list_el_ptr is access list_el_typ;" comes in.
this statement defines a type that will access, or point to, data of type
list_el_typ. now that list_el_ptr is defined, the complete definition of
list_el_type can be written. the end result is a type that is able to point
to another data structure of the same type.

2. the link provided does a decent job of explaining this.

3. next_region is the name of the variable that points to the next data
structure of type list_el_typ. this is the key to creating the linked list.

finally, i don't have a copy of "Writing Testbenches" handy. i will be
shocked and saddened if Janick didn't include a discussion similar to #1
above. so it ain't so!

Michael Jb

Reference: "The Designer's Guide to VHDL", Ashenden, Morgan Kaufman,
p.475-476

----- Original Message -----
> Hi,
>
> in "Writing Testbenches" (Second Edition / Janick Bergeron) there is the
following
> VHDL construct : (page 161)
> process
> subtype byte is std_logic_vector(7 downto 0);
> type region_typ is array(0 to 31) of byte;
>
> type list_el_typ;
> type list_el_ptr is access list_el_typ;
> type list_el_typ is record
> base_addr : natural;
> region : region_typ;
> next_region : list_el_ptr;
> end record;
>
> Some difficulties in understanding:
>
> 1.Why is "type list_el_typ" declared two times ?
>
> 2.What function does "access" have?
>
> 3.I cannot see what type "next_region" has. It has "list_el_ptr". But this
type
> is in turn described with access to the record type ?