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Dear everybody,

I have got a query regarding treatment of variable during synthsis of
behavioural code. In the given example, would the presence of
redundant variable assignment "dummy:=temp" have any impact on the
synthesis of the code. Also, is there any directives to follow for
variables while coding. How is it treated by synthesiser.

for example:

process (.., input_sig, output_sig)
variable temp: std_logic;
variable dummy: std_logic;

begin

temp:= input_sig;
dummy:= temp;
output_sig:=dummy;

.....

end process;

thanks,
Ajay

> I have got a query regarding treatment of variable during synthsis of
> behavioural code. In the given example, would the presence of
> redundant variable assignment "dummy:=temp" have any impact on the
> synthesis of the code. Also, is there any directives to follow for
> variables while coding. How is it treated by synthesiser.
>
> for example:
>
> process (.., input_sig, output_sig)
> variable temp: std_logic;
> variable dummy: std_logic;
>
> begin
>
> temp:= input_sig;
> dummy:= temp;
> output_sig:=dummy;
>
> .....
>
> end process;

This will produce dataflow:
output_sig <= input_sig;

Variables are like temporary references to signals. For ex, temp will be
alias for input_sig, then dummy becomes a reference to the same signal;
finally, output is asserted value of input_sig referenced by dummy.

"Ajay Kumar Mishra" <> escribió en el mensaje
news: m...
> Dear everybody,
>
> I have got a query regarding treatment of variable during synthsis of
> behavioural code. In the given example, would the presence of
> redundant variable assignment "dummy:=temp" have any impact on the
> synthesis of the code. Also, is there any directives to follow for
> variables while coding. How is it treated by synthesiser.
>
> for example:
>
> process (.., input_sig, output_sig)
> variable temp: std_logic;
> variable dummy: std_logic;
>
> begin
>
> temp:= input_sig;
> dummy:= temp;
> output_sig:=dummy;
>
> .....
>
> end process;
>
> thanks,
> Ajay


actually i'd like to know what's the use of variables in synthesis, is it
right to use them? and how?. I mean, i dont think i've ever used variables
in VHDL (not even in non synthesisable code). Just wondering, why would i'd
need them for?, my designs would be better with variables?, am i missing
something good by not using them?. Just asking because i've been seeing a
lot of designs using variables

> actually i'd like to know what's the use of variables in synthesis, is it
> right to use them? and how?. I mean, i dont think i've ever used variables
> in VHDL (not even in non synthesisable code). Just wondering, why would
i'd
> need them for?, my designs would be better with variables?, am i missing
> something good by not using them?. Just asking because i've been seeing a
> lot of designs using variables

Variables are ok in synthesis. They intended to make life easier. Example of
an adder for synthesis:

FUNCTION "+"(a, b : BIT_VECTOR)RETURN BIT_VECTOR IS
VARIABLE s : BIT_VECTOR (a'RANGE);
VARIABLE carry : BIT;
VARIABLE bi : integer; -- Indexes b.
BEGIN
carry := '0';
FOR i IN a'LOW TO a'HIGH LOOP
bi := b'low + (i - a'low);
s(i) := (a(i) XOR b(bi)) XOR carry;
carry := ((a(i) OR b(bi)) AND carry) OR (a(i) AND b(bi));
END LOOP;
RETURN (s);
END "+";

paris wrote:

> actually i'd like to know what's the use of variables in synthesis, is it
> right to use them? and how?. I mean, i dont think i've ever used variables
> in VHDL (not even in non synthesisable code). Just wondering, why would i'd
> need them for?, my designs would be better with variables?, am i missing
> something good by not using them?.

Yes.

You're missing the opportunity to write much better code (without giving
up quality of synthesis results.)

Apart from the obvious "combinatorial" usage of using a variable for an
intermediate result, synthesis tools can also infer flip-flops from
variables when necessary. It's now almost 15 years since this feature
was introduced in Synopsys DC (1.3a or so?).

Real insight comes when you realize you can combine combinatorial
and sequential usage with the same variable.

Do some googling - it has all been discussed before and is available
for those who want to learn.

Regards, Jan

--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Python is fun, and now you can design hardware with it:
http://jandecaluwe.com/Tools/MyHDL/Overview.html

hello Jan,

>synthesis tools can also infer flip-flops from variables when necessary.
Can you give an example Code and little detail about its interpretation by DC?

> Do some googling - it has all been discussed before and is available
> for those who want to learn
Can you tell us about the place where this dicussion has already been held?

thanks and reagrds,
Ajay

Ajay Kumar Mishra wrote:
> hello Jan,
>
>
>>synthesis tools can also infer flip-flops from variables when necessary.
>
> Can you give an example Code and little detail about its interpretation by DC?
>
>
>>Do some googling - it has all been discussed before and is available
>>for those who want to learn
>
> Can you tell us about the place where this dicussion has already been held?

Some google ideas (in Discussion Groups):

group:comp.lang.vhdl Bromley on variable in state machine
group:comp.lang.vhdl Treseler on parallel CRCs
group:comp.lang.vhdl Decaluwe on flip-flop inference from variable
group:comp.lang.verilog Decaluwe on blocking assignments


--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Python is fun, and now you can design hardware with it:
http://jandecaluwe.com/Tools/MyHDL/Overview.html