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"Steve" <> wrote in message news:<c516s3$96f$>...

> Why do people use the block command in VHDL? For example:
>
> state_machine : block
> etc
> etc

It would allow you to limit the scope of
signals and other declarations that would
otherwise span the architecture.

I find it less trouble to use a variable
in process scope for this purpose.

I have never seen a block statement
used outside of a textbook except
as a band-aid for vhdl-87 generate statements.

I expect that someone has found a good use for it.

-- Mike Treseler

Hi,

Why do people use the block command in VHDL? For example:

state_machine : block
etc
etc

I've done a search in google but can find no answers. I was wondering what
affect it has on the code.

Thanks,

Block statement in its simple form creates a
logical level of hierarchy in the VHDL code.
With synthesis commands you can force this to become
an actual level of hierarchy. I have used this
to partition logic that ran into synthesis issues.

Realistically I only use it reactively for
troubleshooting.

Cheers,
Jim

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Steve wrote:
> Hi,
>
> Why do people use the block command in VHDL? For example:
>
> state_machine : block
> etc
> etc
>
> I've done a search in google but can find no answers. I was wondering what
> affect it has on the code.
>
> Thanks,
>
>