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Hi,

I have a problem with accessing a procedure in a special manner:

Some background information:
I want to use a testbench in which I write the valid input data
(16bit) for my VHDL module under test into a ringbuffer. That is my
VHDL module gives out data (16 cleaned bit) after some pipelining
stages.
These output data should be compared with the data I have written into
my ringbuffer (The data in the ringbuffer are unstuffed, that is after
six consecutive ones the following zero is unstuffed. This unstuffing
function is of course also implemented in the VHDL module under test
itself.).
By the means of this object-oriented check I want to verify my module.


Here is my problem:

------------------------------------------------------------
architecture testb of xy is
signal t_Enable_in : std_logic;
signal t_Clk : std_logic;
signal t_Reset : std_logic;
signal t_In_data : std_logic_vector(15 downto 0);
constant history_size : integer := 1024;
signal t_history : std_logic_vector(history_size-1 downto 0);

....
procedure feed(signal d : in std_logic;
signal history : out std_logic_vector(history_size-1
downto 0)) is
variable ptr : integer range 0 to 1023;
variable n : integer range 0 to 6;
begin

if ((n=6) and (d='0')) then
null; --??? Does this exist in VHDL ?
else
history (ptr mod history_size) <= d;
end if;

if d='0' then
n:=0;
else
n:=n+1;
end if;


end feed;

begin
....
-------------------------------------------------------
-------------------------------------------------------
process(t_Reset, t_Clk)
begin
if t_Reset='1' then
t_history <= (others => '0');
elsif rising_edge(t_Clk) then
t_history <= t_history;
if t_Enable_in='1' then
for i in 15 downto 0 loop
feed(d => t_In_data(i),
history => t_history
);
end loop;
end if;
end if;
end process;
-------------------------------------------------------
-------------------------------------------------------
end testb;



I get the following error message (Modelsim5.7e)

# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(134):
The actual for parameter d must denote a static signal name.
# ** Error: H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulation/modelsim/tb_decode_destuff_hs.vhd(146):
VHDL Compiler exiting


How can I change that?

I would appreciate your time and help.

Kind regards
Andres V.

"ALuPin" <> wrote in message
news: om...
> Hi,
>
> I have a problem with accessing a procedure in a special manner:
> procedure feed(signal d : in std_logic;
> signal history : out std_logic_vector(history_size-1
> # ** Error:
H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulat
ion/modelsim/tb_decode_destuff_hs.vhd(134):
> The actual for parameter d must denote a static signal name.
> # ** Error:
H:/EDA/Altera/USB_Extender/16bit_Interface_Module/Decode_destuff_new/simulat
ion/modelsim/tb_decode_destuff_hs.vhd(146):
> VHDL Compiler exiting
>
> How can I change that?

Remove SIGNAL
procedure feed(d : in std_logic; ...

Egbert Molenkamp


..

> procedure feed(signal d : in std_logic;
> signal history : out std_logic_vector(history_size-1
> downto 0)) is
> variable ptr : integer range 0 to 1023;
> variable n : integer range 0 to 6;
> begin
>
> if ((n=6) and (d='0')) then
> null; --??? Does this exist in VHDL ?
> else
> history (ptr mod history_size) <= d;
> end if;
>
> if d='0' then
> n:=0;
> else
> n:=n+1;
> end if;
>
>
> end feed;
>

I didn't check why modelsim complain but your procedure will not work.
Variable inside a procedure are not static. So, each time you call the
procedure feed, n and ptr are recreated and initialize to 0 (begining of the
range).

More, you never assigned a value to ptr.

Yes null exist in VHDL.

You don't need to declare input d as a signal (procedure feed( d: in
std_logic; ...) except if feed is a concurrent procedure.

regards
fe

(ALuPin) wrote in message news:<. com>...
> Hi,
>
> I have a problem with accessing a procedure in a special manner:
>
> for i in 15 downto 0 loop
> feed(d => t_In_data(i),

> I get the following error message (Modelsim5.7e)
>> The actual for parameter d must denote a static signal name.

> How can I change that?

You could do the slice in the procedure.
Also note that procedure variables are not static.
The version below compiles but is incomplete and untested.

-- Mike Treseler
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity xy is
end entity xy;

architecture testb of xy is
signal t_Enable_in : std_logic;
signal t_Clk : std_logic;
signal t_Reset : std_logic;
signal t_In_data : std_logic_vector(15 downto 0);
constant history_size : integer := 1024;
signal t_history : std_logic_vector(history_size-1 downto 0);


procedure feed(bit_ptr : in natural;
h_ptr : in natural;
data : in std_logic_vector;
signal history : out std_logic_vector
(history_size-1 downto 0)
) is
variable d : std_ulogic;
begin
d := data(bit_ptr);
history (h_ptr) <= d;
end feed;

begin
process(t_Reset, t_Clk)
variable bit_ptr_v : natural;
variable history_ptr_v : natural range 0 to 1023;
begin
if t_Reset = '1' then
t_history <= (others => '0');

elsif rising_edge(t_Clk) then
if t_Enable_in = '1' then
for i in 15 downto 0 loop
history_ptr_v := 1 + history_ptr_v;
feed(bit_ptr => i,
h_ptr => history_ptr_v,
data => t_In_data,
history => t_history
);
end loop;
end if;
end if;
end process;
end testb;

> Also note that procedure variables are not static.

Does that mean that variables in processes are static that is that
they keep their value ?
For simulation and also for synthesis? I thought they did not ...


Rgds
Andrés V.

On 7 Apr 2004 23:39:39 -0700, (ALuPin) wrote:

>> Also note that procedure variables are not static.
>
>Does that mean that variables in processes are static that is that
>they keep their value ?

Yes. Processes are elaborated at the beginning of simulation,
procedures are elaborated afresh on entry. Consequently, process
variables are static. By contrast, procedure and function
variables are dynamically elaborated and disappear when the
procedure/function exits.

>For simulation and also for synthesis?

Yes, both. With a few dishonourable exceptions, synthesis
will always deliver the same results as simulation, and will
refuse to process any constructs that can't deliver that
exact match. The exceptions relate to stuff that synthesis
tools think it's safe to ignore, such as time delays and
variable initialisations. Caveat scriptor
--
Jonathan Bromley, Consultant

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Jonathan Bromley a écrit:
> [...] The exceptions relate to stuff that synthesis
> tools think it's safe to ignore, such as time delays and
> variable initialisations. Caveat scriptor

Sensitivity lists, too, perhaps?
Actually, I've been taught some years ago that they ignored them and I
never checked to see if they still did, apart from warning about
incomplete lists.

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