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What is the best available tool for Schemetic editing of VHDL.

My actual planning is to interconnect the blocks(Entitities) Togather.
and generate a good Graphical interpretation to have my logic easily
understandable by my fellow friends.

I am not interested in visualising schmatic of Logic gates within the
Entity. But the interconnects between different entities.

I structured my project in very small entitities, and today i am
finding it diffucult to explain the interconnects to friends. I hope
if i get proper tool it would be easy to expalin the project details.

Atleast Mentor's Renoir used to do the job, but I guess there are many alike
around these days. Many simulation programs (Aldec's active-HDL for one) has
a block editor included...

regrads,
juza

"Purnank" <> wrote in message
news: om...
> What is the best available tool for Schemetic editing of VHDL.
>
> My actual planning is to interconnect the blocks(Entitities) Togather.
> and generate a good Graphical interpretation to have my logic easily
> understandable by my fellow friends.
>
> I am not interested in visualising schmatic of Logic gates within the
> Entity. But the interconnects between different entities.
>
> I structured my project in very small entitities, and today i am
> finding it diffucult to explain the interconnects to friends. I hope
> if i get proper tool it would be easy to expalin the project details.