Please HELP !! register not change

Hi all,

I'm newbie in vhdl coding style, and I'm becoming crazy to understand
some errors that compiler reports.

I'm trying to write a simple code that receive 8 bit data every clock
and try to find the sequence x"00" x"11" x"22", if data in is found it
write back x"aa" x"bb" then start to monitor data in again.

I'm becoming crazy because the compiles tells me that register DATA
and AABB_FOUND never changes and others are NEVER USED!

please could you help?? Which could be the correct VHDL code?

please find below error reports and vhdl code.
Thank you! Hope to learn more from your replies

Regards,
Hikawa



================================================== =======================
* HDL Analysis
*
================================================== =======================
Analyzing Entity <arch> (Architecture <behv>).
INFO:Xst:1304 - Contents of register <aabb_found> in unit <arch> never
changes during circuit operation. The register is replaced by logic.

INFO:Xst:1304 - Contents of register <data> in unit <arch> never
changes during circuit operation. The register is replaced by logic.

Entity <arch> analyzed. Unit <arch> generated.


================================================== =======================
* HDL Synthesis
*
================================================== =======================

Synthesizing Unit <arch>.
Related source file is C:/Programmi/Xilinx/parsec/new.vhd.
WARNING:Xst:646 - Signal <data_in1> is assigned but never used.
WARNING:Xst:646 - Signal <aabb_found> is assigned but never used.
Unit <arch> synthesized.



Here's the simple code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

----------------------------------------------
package pak_array is
type x_array is array(0 to 2) of std_logic_vector(7 downto 0);
constant x: x_array :=
(x"00",x"11",x"22");
end pak_array ;
----------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.pak_array.all;

entity arch is
port (
clock: in std_logic;
reset: in std_logic;
data: inout std_logic_vector(7 downto 0) -- bidirectional port

);
end arch;

-----------------------------------------------

architecture behv of arch is

signal data_in1,
data_in2: std_logic_vector(7 downto 0);

constant reset_active: std_logic := '0'; -- active low reset
constant clock_low: std_logic := '0'; -- active low enable

constant data_in: std_logic_vector(15 downto 0):=x"aabb"; -- sequence
signal aabb_found: std_logic;

begin


-- ********************
-- ** SHIFT REGISTER **
-- ********************

SHIFT_reg: process(clock, reset) is
begin

if (reset=reset_active) then
data_in1<=(others=>'Z');data_in2<=(others=>'Z');
elsif (rising_edge(clock)) then
data_in2<=data;
data_in1<=data_in2;

if ((data_in2 & data_in1)=data_in)
then aabb_found<='1';
end if;

end if;
end process;

DATA_OUT: process(clock) is
begin
if (rising_edge(clock)) then

if aabb_found='1' then
for i in x'range loop
data <= x(i);
end loop;
end if;
end if;
end process;

end behv;

Hayami

On 29 Feb 2004 09:34:51 -0800, (Hayami) wrote:

>Hi all,
>
>I'm newbie in vhdl coding style, and I'm becoming crazy to understand
>some errors that compiler reports.
>
>I'm trying to write a simple code that receive 8 bit data every clock
>and try to find the sequence x"00" x"11" x"22", if data in is found it
>write back x"aa" x"bb" then start to monitor data in again.
>
>I'm becoming crazy because the compiles tells me that register DATA
>and AABB_FOUND never changes and others are NEVER USED!

When does your code set AABB_FOUND to zero? Never!

Consider rewriting the whole design as a state machine.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

Jonathan Bromley <> wrote in message news:<>. ..
> On 29 Feb 2004 09:34:51 -0800, (Hayami) wrote:
>
> >Hi all,
> >
> >I'm newbie in vhdl coding style, and I'm becoming crazy to understand
> >some errors that compiler reports.
> >
> >I'm trying to write a simple code that receive 8 bit data every clock
> >and try to find the sequence x"00" x"11" x"22", if data in is found it
> >write back x"aa" x"bb" then start to monitor data in again.
> >
> >I'm becoming crazy because the compiles tells me that register DATA
> >and AABB_FOUND never changes and others are NEVER USED!
>
> When does your code set AABB_FOUND to zero? Never!
>
> Consider rewriting the whole design as a state machine.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
> Tel: +44 (0)1425 471223 mail:
> Fax: +44 (0)1425 471573 Web: http://www.doulos.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Thank you for your reply

ragards,

Hayami

Hayami