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VHDL - Saving a variable to a text file? |
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#1 |
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Is there anyway to write to a text file in VHDL?
cheers Kwaj |
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#2 |
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Posts: n/a
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A special package exists in VHDL for this reason that is called textio in the std library (usual call looks like: use std.textio.all Have a look into this either on the Net or the VHDL book you're using and I'm sure you'll find what you're looking for. Greg. "Kwaj" <> wrote in message news:403de432$0$22529$. au... > Is there anyway to write to a text file in VHDL? > > cheers > > > Grigorios Angelis |
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