VHDL - help need in conversion problem

02-21-2004, 05:24 AM

hello friends,

i do my ifft implementation with respect to complex number input and
got my output as complex number in simulation side.

Modelsim S.E 5.5 -simulator.

With respect to real type in vhld coding, that one is not synthesised.
so, i'm going to convert the real to std_logic_vector. for that i
fixed by quantization of corresponding value of real type to 8 bit.
ok.

for eg. if i have real value = 0.316 i can represent in bitvector as
"00101000"
and 0 .949= "01111001". if i do some calculations like
a <= 0.316+0.949 <= "00" & "00101000" + "00" & "01111001" =
"0010100001"

0.316+0.949 = 1.265 => "10100001"

both come correct ans.. if suppose some of the carry generate means
what can i do. and if i multiply the sum of number with the some
twiddle factor(that i put in lookup table as std_logic_vector of 8
bit), the total bit will increase at that time manuall calculation of
real converted to bit values and computed result are vary..
for that what i can do .. tell me and give some suggestions...

expecting ur reply
cheers
Senthil.R
MTech vlsi design

senthil

02-26-2004, 03:41 AM

hi ,,
i in need how to convert the real value to bit of 8 bit vector.. ie.,
normalization techniques..
pls give some guidance.
regrds

(senthil) wrote in message news:<. com>...
> hello friends,
>
> i do my ifft implementation with respect to complex number input and
> got my output as complex number in simulation side.
>
> Modelsim S.E 5.5 -simulator.
>
> With respect to real type in vhld coding, that one is not synthesised.
> so, i'm going to convert the real to std_logic_vector. for that i
> fixed by quantization of corresponding value of real type to 8 bit.
> ok.
>
> for eg. if i have real value = 0.316 i can represent in bitvector as
> "00101000"
> and 0 .949= "01111001". if i do some calculations like
> a <= 0.316+0.949 <= "00" & "00101000" + "00" & "01111001" =
> "0010100001"
>
> 0.316+0.949 = 1.265 => "10100001"
>
> both come correct ans.. if suppose some of the carry generate means
> what can i do. and if i multiply the sum of number with the some
> twiddle factor(that i put in lookup table as std_logic_vector of 8
> bit), the total bit will increase at that time manuall calculation of
> real converted to bit values and computed result are vary..
> for that what i can do .. tell me and give some suggestions...
>
> expecting ur reply
> cheers
> Senthil.R
> MTech vlsi design

senthil

02-26-2004, 03:41 AM	#2
senthil Posts: n/a	normalization technique real to bit conversion hi ,, i in need how to convert the real value to bit of 8 bit vector.. ie., normalization techniques.. pls give some guidance. regrds (senthil) wrote in message news:<. com>... > hello friends, > > i do my ifft implementation with respect to complex number input and > got my output as complex number in simulation side. > > Modelsim S.E 5.5 -simulator. > > With respect to real type in vhld coding, that one is not synthesised. > so, i'm going to convert the real to std_logic_vector. for that i > fixed by quantization of corresponding value of real type to 8 bit. > ok. > > for eg. if i have real value = 0.316 i can represent in bitvector as > "00101000" > and 0 .949= "01111001". if i do some calculations like > a <= 0.316+0.949 <= "00" & "00101000" + "00" & "01111001" = > "0010100001" > > 0.316+0.949 = 1.265 => "10100001" > > both come correct ans.. if suppose some of the carry generate means > what can i do. and if i multiply the sum of number with the some > twiddle factor(that i put in lookup table as std_logic_vector of 8 > bit), the total bit will increase at that time manuall calculation of > real converted to bit values and computed result are vary.. > for that what i can do .. tell me and give some suggestions... > > expecting ur reply > cheers > Senthil.R > MTech vlsi design senthil

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02-21-2004, 05:24 AM	#1
	help need in conversion problem hello friends, i do my ifft implementation with respect to complex number input and got my output as complex number in simulation side. Modelsim S.E 5.5 -simulator. With respect to real type in vhld coding, that one is not synthesised. so, i'm going to convert the real to std_logic_vector. for that i fixed by quantization of corresponding value of real type to 8 bit. ok. for eg. if i have real value = 0.316 i can represent in bitvector as "00101000" and 0 .949= "01111001". if i do some calculations like a <= 0.316+0.949 <= "00" & "00101000" + "00" & "01111001" = "0010100001" 0.316+0.949 = 1.265 => "10100001" both come correct ans.. if suppose some of the carry generate means what can i do. and if i multiply the sum of number with the some twiddle factor(that i put in lookup table as std_logic_vector of 8 bit), the total bit will increase at that time manuall calculation of real converted to bit values and computed result are vary.. for that what i can do .. tell me and give some suggestions... expecting ur reply cheers Senthil.R MTech vlsi design senthil