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VHDL - Are generics and ports static names?

 
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Old 02-20-2004, 07:48 PM   #1
Default Are generics and ports static names?


LRM 4.3.2.2, p. 63, line 508:

"Each association element that associates a slice or subelement (or slice
thereof) of an interface object must identify the formal with a locally
static name."

LRM 6.1, p. 84, line 46:

"a name is said to be a locally static name if and only if one of the
following conditions hold:

The name is a simple name ... that is not an alias and that does not denote
.... an object ...
"

LRM 4.3, p. 53, lines 94-100:

"An object is one of the following:

....

A formal port
....
A local port
"

With these definitions, how is the following legal:

U1: FOO port map(BAR(3) => BAZ);

BAR is an object, therefore not a locally static name.

Did the LRM really mean to say that the slice/index expression must be
a locally static expression? That makes sense.



David Jones
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