4 stage register or fifo

Hello,

I need a vhdl entity that allows me to write four x-bit values on a
periodic write signal and then read them out sequentially (in 4 clock
cycles) base on a read signal.

So you would have a diagram like something like this:

_ _ _ _
write _| |______| |______| |______| |________

value a b c d
_
read _____________________________________| |_______

value a b c d


Is this best implemented in a single small 4 word fifo or is there
another better approache?

Salman

salman sheikh

salman sheikh wrote:
>
> Hello,
>
> I need a vhdl entity that allows me to write four x-bit values on a
> periodic write signal and then read them out sequentially (in 4 clock
> cycles) base on a read signal.
>
> So you would have a diagram like something like this:
>
> _ _ _ _
> write _| |______| |______| |______| |________
>
> value a b c d
> _
> read _____________________________________| |_______
>
> value a b c d
>
>
> Is this best implemented in a single small 4 word fifo or is there
> another better approache?
>

Do you need al the features of a FIFO? i.e:
Do you need to make use of 'empty' or 'full' flags ?
Do you always write _exactly_ four values before reading them out ?
Or may it happen that you write 6, then read out 4, then write in 2, then read
out 4...
basically,
What is the environment really requesting from your device ?

I definetly can help you, but you need to provide more info,

TechConSoul.

Francisco Camarero

Thanks for your reply. I have posted on this and other newsgroups with
questions that never go answered or replied to. I appreciate your time.

Don't need a empty or full flag. I just need to store four 35-bit words
somewhere and then, after waiting for another process to complete with
a valid signal, read them out sequentially in four consecutive clock
cycles, the first value written read out first. Maybe a fifo is overkill?

Salman

Francisco Camarero wrote:
> salman sheikh wrote:
>
>>Hello,
>>
>>I need a vhdl entity that allows me to write four x-bit values on a
>>periodic write signal and then read them out sequentially (in 4 clock
>>cycles) base on a read signal.
>>
>>So you would have a diagram like something like this:
>>
>> _ _ _ _
>>write _| |______| |______| |______| |________
>>
>>value a b c d
>> _
>>read _____________________________________| |_______
>>
>>value a b c d
>>
>>
>>Is this best implemented in a single small 4 word fifo or is there
>>another better approache?
>>
>
>
> Do you need al the features of a FIFO? i.e:
> Do you need to make use of 'empty' or 'full' flags ?
> Do you always write _exactly_ four values before reading them out ?
> Or may it happen that you write 6, then read out 4, then write in 2, then read
> out 4...
> basically,
> What is the environment really requesting from your device ?
>
> I definetly can help you, but you need to provide more info,
>
> TechConSoul.

salman sheikh