Using loop vars in a testbench

Is it possible to assign the value of a loop variable to a
std_logic_vector? I'm trying to make the following code work:

--A : in std_logic_vector(7 downto 0);

for i in 0 to 15 loop
A <= --gets value of i
wait for 20 ns;
loop;


Does anyone know the library and type conversion function that I can use to
assign the loop variable (which I think is of type integer) to A, which is
type std_logic_vector, width=8?

Thanks.

sku11monkey

http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#4.8.1
Will answer all your question.

Egbert Molenkamp

"sku11monkey" <> schreef in bericht
news:YrKdnRZcXYOVg6zdRVn-...
> Is it possible to assign the value of a loop variable to a
> std_logic_vector? I'm trying to make the following code work:
>
> --A : in std_logic_vector(7 downto 0);
>
> for i in 0 to 15 loop
> A <= --gets value of i
> wait for 20 ns;
> loop;
>
>
> Does anyone know the library and type conversion function that I can use
to
> assign the loop variable (which I think is of type integer) to A, which is
> type std_logic_vector, width=8?
>
> Thanks.

Egbert Molenkamp

i) Your declaration (A: in std_logic_vector(7 downto 0) implies that A is
an input port to the entity (?)
You cannot assign to input ports.

ii) Assuming the above is just a typing error the following code seems to
compile fine for me:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

Grigorios Angelis