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VHDL verilog mixed design, strange problem

 
 
Akshaye
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      02-06-2004
Hi,

I had this wierd issue with vhdl-verilog co-simulation.

I have a net which is driven in VHDL and is used as an input to 2
verilog designs which are instantiated in this VHDL block.

|-----
|----->|verilog A
| |-----
VHDL ----|
| |-----
|----->|verilog B
|-----

The net is directly used on ports on the verilog modules. Now if i
assign this internal net in "verilog A" module via PLI, a strange
thing happens in the simulator. The net inside verilog A is assigned
this value, the net inside verilog B is assigned this value(wierd?)
but the top level net in VHDL does not get this value!

I have no issue with the VHDL net not getting the assigned
value(because its direction is opposite), but what complicates
debugging is that it is assigned in verilog B.

Is this some optimisation in the simulator which moves this net node
from VHDL to verilog possibly to reduce VHDL to verilog boundary
signals? Can somebody provide an expaination for this? is it simulator
dependent?

Thanks in advance.
 
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Hemant Gupta
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Posts: n/a
 
      02-09-2004
This should be simulator dependent.

regards,

Akshaye wrote:

> Hi,
>
> I had this wierd issue with vhdl-verilog co-simulation.
>
> I have a net which is driven in VHDL and is used as an input to 2
> verilog designs which are instantiated in this VHDL block.
>
> |-----
> |----->|verilog A
> | |-----
> VHDL ----|
> | |-----
> |----->|verilog B
> |-----
>
> The net is directly used on ports on the verilog modules. Now if i
> assign this internal net in "verilog A" module via PLI, a strange
> thing happens in the simulator. The net inside verilog A is assigned
> this value, the net inside verilog B is assigned this value(wierd?)
> but the top level net in VHDL does not get this value!
>
> I have no issue with the VHDL net not getting the assigned
> value(because its direction is opposite), but what complicates
> debugging is that it is assigned in verilog B.
>
> Is this some optimisation in the simulator which moves this net node
> from VHDL to verilog possibly to reduce VHDL to verilog boundary
> signals? Can somebody provide an expaination for this? is it simulator
> dependent?
>
> Thanks in advance.


 
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