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asynchronous counter an Xilinx FPGA for a newbie

 
 
Georges Konstantinidis
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Posts: n/a
 
      01-30-2004
Dear all
I'm deseprately trying to make an asynchronous counter to count the number
of inputs I have on a pin. I also want a reset input.
I copied the last version of my code at this e-mail .
The synthesis looks good but an error comes at the implementation design. I
don't kow to to do any more.
Thank you for fixing my bugs, Georges.


library ieee;
use ieee.std_logic_1164.all;

entity counter is
port(Load, Rst: in std_logic;
LED: out std_logic_vector(0 to 7)
);
end counter;

architecture behaviour of counter is
signal Qreg: std_logic_vector(0 to 7);

begin
process(Rst, Load)
begin
if Rst = '1' then -- Async reset
Qreg <= "00000000";
elsif Load='1' then
Qreg<=Qreg+1;
end if;

end process;

LED <= Qreg;

end behaviour;


 
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Egbert Molenkamp
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Posts: n/a
 
      01-30-2004
Your synthesis tool does not synthesize:
> process(Rst, Load)
> begin
> if Rst = '1' then -- Async reset
> Qreg <= "00000000";
> elsif Load='1' then
> Qreg<=Qreg+1;
> end if;


But it synthesizes it with a different sensitivity list:
process(Rst, Load, QREG)

If you simulate (before synthesis) the process with this sensitive list
you will notice the loop if LOAD='1' and rst='0'.

I'm not sure if you want a latch, but a flipflop solves the problem.
Replace
> elsif Load='1' then

with
elsif rising_edge(Load) then

Egbert Molenkamp

"Georges Konstantinidis" <(E-Mail Removed)> schreef in
bericht news:401ab556$0$777$(E-Mail Removed)...
> Dear all
> I'm deseprately trying to make an asynchronous counter to count the number
> of inputs I have on a pin. I also want a reset input.
> I copied the last version of my code at this e-mail .
> The synthesis looks good but an error comes at the implementation design.

I
> don't kow to to do any more.
> Thank you for fixing my bugs, Georges.
>
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity counter is
> port(Load, Rst: in std_logic;
> LED: out std_logic_vector(0 to 7)
> );
> end counter;
>
> architecture behaviour of counter is
> signal Qreg: std_logic_vector(0 to 7);
>
> begin
> process(Rst, Load)
> begin
> if Rst = '1' then -- Async reset
> Qreg <= "00000000";
> elsif Load='1' then
> Qreg<=Qreg+1;
> end if;
>
> end process;
>
> LED <= Qreg;
>
> end behaviour;
>
>



 
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Andy Peters
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Posts: n/a
 
      01-30-2004
"Georges Konstantinidis" <(E-Mail Removed)> wrote in message news:<401ab556$0$777$(E-Mail Removed)>...
> Dear all
> I'm deseprately trying to make an asynchronous counter to count the number
> of inputs I have on a pin. I also want a reset input.
> I copied the last version of my code at this e-mail .
> The synthesis looks good but an error comes at the implementation design. I
> don't kow to to do any more.
> Thank you for fixing my bugs, Georges.
>
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity counter is
> port(Load, Rst: in std_logic;
> LED: out std_logic_vector(0 to 7)
> );
> end counter;
>
> architecture behaviour of counter is
> signal Qreg: std_logic_vector(0 to 7);
>
> begin
> process(Rst, Load)
> begin
> if Rst = '1' then -- Async reset
> Qreg <= "00000000";
> elsif Load='1' then
> Qreg<=Qreg+1;
> end if;
>
> end process;
>
> LED <= Qreg;
>
> end behaviour;


Why do you want to do an async counter? No clock available?

What is the implementation error? (Actually, I know what it is -- but
I want to know what you think it is.)

Think about:

What happens if neither Rst nor Load are asserted?

--a
 
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Georges Konstantinidis
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Posts: n/a
 
      01-31-2004
What do you mean by saying "asserted"?
"Andy Peters" <(E-Mail Removed)> a écrit dans le message de
news:(E-Mail Removed) om...
> "Georges Konstantinidis" <(E-Mail Removed)> wrote in

message news:<401ab556$0$777$(E-Mail Removed)>...
> > Dear all
> > I'm deseprately trying to make an asynchronous counter to count the

number
> > of inputs I have on a pin. I also want a reset input.
> > I copied the last version of my code at this e-mail .
> > The synthesis looks good but an error comes at the implementation

design. I
> > don't kow to to do any more.
> > Thank you for fixing my bugs, Georges.
> >
> >
> > library ieee;
> > use ieee.std_logic_1164.all;
> >
> > entity counter is
> > port(Load, Rst: in std_logic;
> > LED: out std_logic_vector(0 to 7)
> > );
> > end counter;
> >
> > architecture behaviour of counter is
> > signal Qreg: std_logic_vector(0 to 7);
> >
> > begin
> > process(Rst, Load)
> > begin
> > if Rst = '1' then -- Async reset
> > Qreg <= "00000000";
> > elsif Load='1' then
> > Qreg<=Qreg+1;
> > end if;
> >
> > end process;
> >
> > LED <= Qreg;
> >
> > end behaviour;

>
> Why do you want to do an async counter? No clock available?
>
> What is the implementation error? (Actually, I know what it is -- but
> I want to know what you think it is.)
>
> Think about:
>
> What happens if neither Rst nor Load are asserted?
>
> --a



 
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Andrew Greensted
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Posts: n/a
 
      02-02-2004
Try this:

library ieee;
use ieee.std_logic_1164.all;

entity counter is
port( Load: in std_logic;
Rst: in std_logic;
LED: out std_logic_vector(0 to 7));

end counter;

architecture behaviour of counter is
begin

cnt : process(Rst, Load)

variable count : std_logic_vector(7 downto 0);

begin

if (Rst = '1' then) then
count := "00000000";
else if (Load'event and Load='1') then
count := count + 1;
end if;

LED <= count;

end process cnt;

end behaviour;

Now make sure that Load is 'locked' to a clock input on the FPGA, or
you'll probably get complaints of a logic line driving clock inputs.
Try using something like:

attribute LOC : string;
attribute LOC of signal Load : signal is "pin number";

Every time that a rising edge of Lock occurs, the variable count is
incremented. LED will be loaded with the value of count each time the
process 'runs' (I assume this is what you want?).


Georges Konstantinidis wrote:
> What do you mean by saying "asserted"?
> "Andy Peters" <(E-Mail Removed)> a écrit dans le message de
> news:(E-Mail Removed) om...
>
>>"Georges Konstantinidis" <(E-Mail Removed)> wrote in

>
> message news:<401ab556$0$777$(E-Mail Removed)>...
>
>>>Dear all
>>>I'm deseprately trying to make an asynchronous counter to count the

>
> number
>
>>>of inputs I have on a pin. I also want a reset input.
>>>I copied the last version of my code at this e-mail .
>>>The synthesis looks good but an error comes at the implementation

>
> design. I
>
>>>don't kow to to do any more.
>>>Thank you for fixing my bugs, Georges.
>>>
>>>
>>>library ieee;
>>>use ieee.std_logic_1164.all;
>>>
>>>entity counter is
>>> port(Load, Rst: in std_logic;
>>> LED: out std_logic_vector(0 to 7)
>>>);
>>>end counter;
>>>
>>>architecture behaviour of counter is
>>> signal Qreg: std_logic_vector(0 to 7);
>>>
>>>begin
>>> process(Rst, Load)
>>> begin
>>> if Rst = '1' then -- Async reset
>>> Qreg <= "00000000";
>>> elsif Load='1' then
>>> Qreg<=Qreg+1;
>>> end if;
>>>
>>> end process;
>>>
>>> LED <= Qreg;
>>>
>>>end behaviour;

>>
>>Why do you want to do an async counter? No clock available?
>>
>>What is the implementation error? (Actually, I know what it is -- but
>>I want to know what you think it is.)
>>
>>Think about:
>>
>>What happens if neither Rst nor Load are asserted?
>>
>>--a

>
>
>

 
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Andy Peters
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Posts: n/a
 
      02-02-2004
"Georges Konstantinidis" <(E-Mail Removed)> wrote in message news:<401c1026$0$13244$(E-Mail Removed)>...

> What do you mean by saying "asserted"?


"Asserted" means "put into the active state."

It's a very common term. It's useful because it nicely ignores the
detail of whether the signal is active low or active high.

--a
 
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Georges Konstantinidis
Guest
Posts: n/a
 
      02-02-2004
Thanks for the info.
"Andy Peters" <(E-Mail Removed)> a écrit dans le message de
news:(E-Mail Removed) om...
> "Georges Konstantinidis" <(E-Mail Removed)> wrote in

message news:<401c1026$0$13244$(E-Mail Removed)>...
>
> > What do you mean by saying "asserted"?

>
> "Asserted" means "put into the active state."
>
> It's a very common term. It's useful because it nicely ignores the
> detail of whether the signal is active low or active high.
>
> --a



 
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Georges Konstantinidis
Guest
Posts: n/a
 
      02-02-2004
Hello Andrew,
I was endeed using a "normal I/O port" which is synchronous or asynchronous
according to the datasheets. I should be able to use it.
Or I miss something.
I found also a template in ISE called "debounce circuit" which seems to
work.
In any case I will also try what you said
Thanks everyone for you cooperation, Georges.



"Andrew Greensted" <(E-Mail Removed)> a écrit dans le message de
news:bvlerm$crt$(E-Mail Removed)...
> Try this:
>
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity counter is
> port( Load: in std_logic;
> Rst: in std_logic;
> LED: out std_logic_vector(0 to 7));
>
> end counter;
>
> architecture behaviour of counter is
> begin
>
> cnt : process(Rst, Load)
>
> variable count : std_logic_vector(7 downto 0);
>
> begin
>
> if (Rst = '1' then) then
> count := "00000000";
> else if (Load'event and Load='1') then
> count := count + 1;
> end if;
>
> LED <= count;
>
> end process cnt;
>
> end behaviour;
>
> Now make sure that Load is 'locked' to a clock input on the FPGA, or
> you'll probably get complaints of a logic line driving clock inputs.
> Try using something like:
>
> attribute LOC : string;
> attribute LOC of signal Load : signal is "pin number";
>
> Every time that a rising edge of Lock occurs, the variable count is
> incremented. LED will be loaded with the value of count each time the
> process 'runs' (I assume this is what you want?).
>
>
> Georges Konstantinidis wrote:
> > What do you mean by saying "asserted"?
> > "Andy Peters" <(E-Mail Removed)> a écrit dans le message de
> > news:(E-Mail Removed) om...
> >
> >>"Georges Konstantinidis" <(E-Mail Removed)> wrote in

> >
> > message news:<401ab556$0$777$(E-Mail Removed)>...
> >
> >>>Dear all
> >>>I'm deseprately trying to make an asynchronous counter to count the

> >
> > number
> >
> >>>of inputs I have on a pin. I also want a reset input.
> >>>I copied the last version of my code at this e-mail .
> >>>The synthesis looks good but an error comes at the implementation

> >
> > design. I
> >
> >>>don't kow to to do any more.
> >>>Thank you for fixing my bugs, Georges.
> >>>
> >>>
> >>>library ieee;
> >>>use ieee.std_logic_1164.all;
> >>>
> >>>entity counter is
> >>> port(Load, Rst: in std_logic;
> >>> LED: out std_logic_vector(0 to 7)
> >>>);
> >>>end counter;
> >>>
> >>>architecture behaviour of counter is
> >>> signal Qreg: std_logic_vector(0 to 7);
> >>>
> >>>begin
> >>> process(Rst, Load)
> >>> begin
> >>> if Rst = '1' then -- Async reset
> >>> Qreg <= "00000000";
> >>> elsif Load='1' then
> >>> Qreg<=Qreg+1;
> >>> end if;
> >>>
> >>> end process;
> >>>
> >>> LED <= Qreg;
> >>>
> >>>end behaviour;
> >>
> >>Why do you want to do an async counter? No clock available?
> >>
> >>What is the implementation error? (Actually, I know what it is -- but
> >>I want to know what you think it is.)
> >>
> >>Think about:
> >>
> >>What happens if neither Rst nor Load are asserted?
> >>
> >>--a

> >
> >
> >



 
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Sajan
Guest
Posts: n/a
 
      02-03-2004
First of all , when you say that you are implementing a counter,
what are you going to count???????

assuming whatever you are going to count is A, then
use this code to increment the count
if A'event and A = '1' -- or A = '0' whatever be the case
count := count + 1;
end if;

or else you might endup counting something else or endup in a
infinite loop as u see to be now.




"Georges Konstantinidis" <(E-Mail Removed)> wrote in message news:<401e8f16$0$322$(E-Mail Removed)>...
> Thanks for the info.
> "Andy Peters" <(E-Mail Removed)> a écrit dans le message de
> news:(E-Mail Removed) om...
> > "Georges Konstantinidis" <(E-Mail Removed)> wrote in

> message news:<401c1026$0$13244$(E-Mail Removed)>...
> >
> > > What do you mean by saying "asserted"?

> >
> > "Asserted" means "put into the active state."
> >
> > It's a very common term. It's useful because it nicely ignores the
> > detail of whether the signal is active low or active high.
> >
> > --a

 
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Georges Konstantinidis
Guest
Posts: n/a
 
      02-03-2004
I want to count pulses coming from outside the FPGA (Spartan IIe on the
Burched board) and displays the valus on a 7 digits segment.
I tried already your code. the synthesis works, but not the implementation
design. I created an UCF file to assign the pin, maybe this file creates
problem.
I do not know at which moment of the process I should assign the pins.
Georges.



"Sajan" <(E-Mail Removed)> a écrit dans le message de
news:(E-Mail Removed) om...
> First of all , when you say that you are implementing a counter,
> what are you going to count???????
>
> assuming whatever you are going to count is A, then
> use this code to increment the count
> if A'event and A = '1' -- or A = '0' whatever be the case
> count := count + 1;
> end if;
>
> or else you might endup counting something else or endup in a
> infinite loop as u see to be now.
>
>
>
>
> "Georges Konstantinidis" <(E-Mail Removed)> wrote in

message news:<401e8f16$0$322$(E-Mail Removed)>...
> > Thanks for the info.
> > "Andy Peters" <(E-Mail Removed)> a écrit dans le message de
> > news:(E-Mail Removed) om...
> > > "Georges Konstantinidis" <(E-Mail Removed)> wrote in

> > message news:<401c1026$0$13244$(E-Mail Removed)>...
> > >
> > > > What do you mean by saying "asserted"?
> > >
> > > "Asserted" means "put into the active state."
> > >
> > > It's a very common term. It's useful because it nicely ignores the
> > > detail of whether the signal is active low or active high.
> > >
> > > --a



 
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