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generic vector

 
 
valentin tihomirov
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      01-30-2004
I'm trying to do the following:

entity LFSR is
generic (
SIZE : Integer := 8;
SEED: std_logic_vector(SIZE-1 downto 0) := (othres => '1')
);
port (

The seed should be loaded into FFs on reset. The problem is that SIZE
generic cannot be used in SEED declaration. Am I doing something wrong?


 
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MK
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      02-02-2004

"valentin tihomirov" <(E-Mail Removed)> wrote in
message news:bve38p$riekr$(E-Mail Removed)-berlin.de...
> I'm trying to do the following:
>
> entity LFSR is
> generic (
> SIZE : Integer := 8;
> SEED: std_logic_vector(SIZE-1 downto 0) := (othres => '1')
> );
> port (
>
> The seed should be loaded into FFs on reset. The problem is that SIZE
> generic cannot be used in SEED declaration. Am I doing something wrong?
>
>

"generic ( ... )" statement create declaration region - you cannot use
any generic declared inside until region is closed (you can use generics in
port ( ... ) region).

regards,
MK.


 
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Jonathan Bromley
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      02-02-2004
"valentin tihomirov" <(E-Mail Removed)> wrote
in message news:bve38p$riekr$(E-Mail Removed)-berlin.de...

hi Valentin,

I thought we had already talked about some solutions to this?

> I'm trying to do the following:
>
> entity LFSR is
> generic (
> SIZE : Integer := 8;
> SEED: std_logic_vector(SIZE-1 downto 0) := (othres => '1')
> );
> port (
>
> The seed should be loaded into FFs on reset. The problem is that SIZE
> generic cannot be used in SEED declaration. Am I doing something wrong?


As MK pointed out, you can't use a generic within the same generic
declaration.

However, there is a much simpler, much nicer solution to your
problem.

entity LFSR is
generic (
SEED: std_logic_vector := "11111111"
);
port (

Now, within the design you can use SEED'LENGTH wherever you would
have used your unnecessary generic SIZE. Or even...

architecture xxx of LFSR is
constant SIZE: positive := SEED'LENGTH;
signal LFSR_Register: std_logic_vector(SEED'RANGE);
begin
...

Now you can configure each instance of LFSR with a single
generic map - the number of bits in the generic sets SIZE,
and its value sets SEED.

This leaves you with a different problem: In most cases
I guess you want to configure SIZE through a generic, but
you want the seed automatically set to (others=>'1').
This is easily done by adding a wrapper around LFSR:

entity LFSR_All_Ones_Seed is
generic (
SIZE: positive := 8
);
port (
clk: in std_logic;
...
);
end;
architecture XXX of LFSR_All_Ones_Seed is
constant SEED: std_logic_vector(SIZE-1 downto 0) := (others => '1');
component LFSR
generic (
SEED: std_logic_vector
);
port (
...
end component;
begin
-- Nothing here except an instance of the standard LFSR:
LFSR_Instance: LFSR
generic map (SEED => SEED)
port map (
clk => clk,
...
end;

Hope this helps
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: http://www.velocityreviews.com/forums/(E-Mail Removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



 
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valentin tihomirov
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      02-03-2004
> "generic ( ... )" statement create declaration region - you cannot use
> any generic declared inside until region is closed (you can use generics

in
> port ( ... ) region).


Why does VHDL prohibit doing this? Why does VHDL prohibit negative-index
loops while most general-purpose languages support both? Is it because VHDL
is not matured language and things will change soon or there are any
fundamental barriers? Many thanks.


 
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Jonathan Bromley
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      02-03-2004
"valentin tihomirov" <(E-Mail Removed)> wrote
in message news:bvnrt5$tf4b6$(E-Mail Removed)-berlin.de...

> Why does VHDL prohibit negative-index loops [...] ?


Can you provide an example of this restriction?
I am not aware of it. Do the following not
meet your needs?

for i in -3 to -1 loop ...

for i in 10 downto -20 loop ...

Perhaps you are concerned that std_logic_vector can
take only non-negative subscripts. This is simply
because it is defined as "array (NATURAL range <>) of...".
You are quite entitled to define an array indexed by
integer if you so wish, and such an array may have
negative subscripts. C-like languages lack this
flexibility.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (E-Mail Removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



 
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valentin tihomirov
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      02-03-2004
Here is an example of negative index I'm talking about

@CLK:
Buf := Rx & Buf(WIDTH-2 downto 1);

I'm trying to shift buffer to right. But this neat 1-line code should be
modified and becomes cumbersome because the generic WIDTH parameter can be
any integer > 0. This means if WIDTH = 1 I'm getting (-1 downto 1) loop and
when WIDTH = 2 I'm getting (0 downto 1 loop). Both these cases should be
handeled specially in VHDL (using if clause). In Pascal/C and any other
general-purpose language negative loops like

for I := WIDTH-2 downto 1 do
...

are ignored for width < 2 cases. VHDL compiler could ignore as well, but it
complains "negative index" instead.




 
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Jonathan Bromley
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      02-03-2004
"valentin tihomirov" <(E-Mail Removed)>
wrote in message news:bvofpk$upm9b$(E-Mail Removed)-berlin.de...

> Here is an example of negative index I'm talking about
>
> @CLK:
> Buf := Rx & Buf(WIDTH-2 downto 1);


THAT IS NOT A LOOP!

> I'm trying to shift buffer to right. But this neat 1-line code should be
> modified and becomes cumbersome because the generic WIDTH parameter can be
> any integer > 0. This means if WIDTH = 1 I'm getting (-1 downto 1) loop

and
> when WIDTH = 2 I'm getting (0 downto 1 loop). Both these cases should be
> handeled specially in VHDL (using if clause). In Pascal/C and any other
> general-purpose language negative loops like
>
> for I := WIDTH-2 downto 1 do
> ...
>
> are ignored for width < 2 cases. VHDL compiler could ignore as well, but

it
> complains "negative index" instead.


No, no, no. VHDL also ignores procedural loops with no trips,
like that. You can't take slices of an array in C anyway!

Please now, tell me what you want to happen in the example...

I guess you are trying to shift the single bit Rx into the multi-bit
register Buf. If that's true, your code is wrong, I think.

Presumably Buf is declared
Buf: std_logic_vector(WIDTH-1 downto 0);

If this is right, and Rx is a single bit, then

Buf := Rx & Buf(WIDTH-2 downto 1)

is erroneous because the right-hand side is one bit shorter than
the left!

However, let's suppose that your Rx is in fact 2 bits. In that
case it would be ridiculous to have WIDTH < 2, because you could
never assign Rx into Buf!

I guess your shift operation should be correctly coded:

Buf := Rx & Buf(WIDTH-1 downto 1);

This will work correctly for any WIDTH >= 2.

However, if WIDTH=1 you have a problem because the shift register
is not a shift register at all, but merely a simple register.
Strictly speaking VHDL should handle this, because Buf(0 downto 1)
should be a null range, but some tools complain about it. This
is the one and only case where your argument might have some force.
If you really must do such a thing, then simply USE a loop!

This code assumes that Buf was declared with a DOWNTO range - it is
possible, but a little harder, to write code that works correctly
with both TO and DOWNTO ranges, but I don't think that is necessary.

for i in Buf'RANGE loop
if i = Buf'LEFT then
Buf(i) := Rx;
else
Buf(i) := Buf(i+1);
end if;
end loop;

I agree that this is not so pretty as the single-line slice, but
it's easy to understand, fairly efficient in simulation, and
for synthesis it is just as good as the other form.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (E-Mail Removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



 
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valentin tihomirov
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      02-03-2004
Please, foregive me. I should be more specific. RXix is one-bit signal and
BUF is a bit-vector.


 
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