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Portability

 
 
Francisco Rodriguez
Guest
Posts: n/a
 
      01-21-2004
Hi Steve

If you directly instantiate the block ram as a component, then that's
obviously non-portable code.

But yes, you can create a VHDL process using the XST provided template
to ensure the synthesizer will infer a block ram instead of distributed
memory
if you make use of the corresponding XST option (synthesizer options->HDL
options->RAM style = block).
The VHDL templates are on the "HDL Coding Techniques" section of the XST
user guide.

As long as you use block rams by inferring them from your source,
the code will be portable to a different architecture.

Regards
Francisco

"Steve" <(E-Mail Removed)> escribió en el mensaje
news:bumi89$mi7$(E-Mail Removed)...
> Hi,
>
> I'm quite new to VHDL so this question maybe quite basic.
>
> I'm desiging a system using an XILINX Spartan FPGA and in my system I need
> to store 1024 bytes of data. Originally I planned to create an array of
> 1024 bytes and store the data inside it. But such a large array is too

big
> for the FPGA. The FPGA contains several block ram components which suit

my
> storage needs. My question is, if I use the block RAM's will my VHDL code
> still be portable? By portable I mean will it synthersize for devices

other
> than my FPGA?
>
> Thanks for any info,
>
>



 
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Steve
Guest
Posts: n/a
 
      01-22-2004
Hi,

I'm quite new to VHDL so this question maybe quite basic.

I'm desiging a system using an XILINX Spartan FPGA and in my system I need
to store 1024 bytes of data. Originally I planned to create an array of
1024 bytes and store the data inside it. But such a large array is too big
for the FPGA. The FPGA contains several block ram components which suit my
storage needs. My question is, if I use the block RAM's will my VHDL code
still be portable? By portable I mean will it synthersize for devices other
than my FPGA?

Thanks for any info,


 
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fabbl
Guest
Posts: n/a
 
      01-23-2004
Hi Steve,
When I write a design document I note target dependencies and write a
risk/mitigation analysis along side. Portability is essential to cost
reduction etc. Alternately the function can be described externally (if
allowed), home-grown or a commitment can be made to the part. Often, the
later is the choice if time doesn' permit. Leave yourself an "out" if you
can.

Any targeted core technology (ie Coregen) is married to the targets
resources to make it work. If you need more flexibility. Do what is
suggested above.


"Steve" <(E-Mail Removed)> wrote in message
news:bumi89$mi7$(E-Mail Removed)...
> Hi,
>
> I'm quite new to VHDL so this question maybe quite basic.
>
> I'm desiging a system using an XILINX Spartan FPGA and in my system I need
> to store 1024 bytes of data. Originally I planned to create an array of
> 1024 bytes and store the data inside it. But such a large array is too

big
> for the FPGA. The FPGA contains several block ram components which suit

my
> storage needs. My question is, if I use the block RAM's will my VHDL code
> still be portable? By portable I mean will it synthersize for devices

other
> than my FPGA?
>
> Thanks for any info,
>
>
>



 
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