Getting up-to-date libraries for timing simulation

01-01-2004

I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting
VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown
identifier "X_ROC"* error. X_ROC is the only primitive that cannot be found
in the SIMPRIM library provided with ActiveHDL. What is the standard
procedure of getting up-to-date libraries: asking library sources from
Xilinx or precompiled .lib file from Aldec? Simulator vendors somehow
optimize pre-compiled libraries.

01-05-2004

valentin tihomirov wrote:
> I have compiled a design with XSE 6.1i. It produced post-synthesis/fitting
> VHDL model. ActiveHDL 6.1 simulator fails compilation with *Unknown
> identifier "X_ROC"* error.

Consider writing your own vhdl code and
siming it before synthesis.

-- Mike Treseler

01-05-2004

> Consider writing your own vhdl code and
> siming it before synthesis.
Excuse me, what does this mean? BTW, I have resolved the problem by
downloading last version (6.2) of SW from Aldec.

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
How to perform a timing simulation in Modelsim with QuartusII output file ?	ALuPin	VHDL	13	11-27-2008 05:05 PM
Problem with post-route simulation / timing simulation	jasperng	VHDL	0	11-27-2008 06:23 AM
Question about real-time timing simulation	systolic	VHDL	0	10-04-2004 10:42 PM
How to obtain original input/output signal name from SDF Timing Simulation within Modelsim?	Chao	VHDL	4	06-14-2004 04:09 PM
back-annotation SDF Timing Simulation	Chao	VHDL	1	05-06-2004 05:23 PM