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boolean to std_logic

 
 
valentin tihomirov
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      12-31-2003
Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
Should I write my function? Why there isn't implicit sythax of that?


 
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Ray Andraka
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      12-31-2003
This is actually a spin-off of a topic that is being discussed in the VHDL
standards committee. The rub is that True does not always equate to
'1'..negative logic systems use '0' = true. A function to do this is
straight-forward to write.

valentin tihomirov wrote:

> Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
> Should I write my function? Why there isn't implicit sythax of that?


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valentin tihomirov
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      01-01-2004
Thanks. I've got a more general answer regarding VHDL. VHDL is a strongly
typed language; thus, all the type conversions should be explicit. It should
save one's life, some day. In addition, I've discovered a Boolean type that
makes code much cleaner allowing to bypass the conversion in most cases.


 
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Mike Treseler
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      01-05-2004
valentin tihomirov wrote:
> Is there any standard package that can convert TRUE to '1' and FALSE to '0'?
> Should I write my function?


yes:

http://groups.google.com/groups?q=vhdl+active_high

-- Mike Treseler

 
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