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Out of phase

 
 
Steve
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      12-30-2003
Hi everyone,

I need to generate a square wave (CLK_OUT) which is 270 degree's out of
phase with another square wave (CLK_IN). I guess this is a simple thing to
do. Can anyone recommend some simple VHDL code or a state machine to do
such a thing?

Thanks in advance,



 
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jussi l
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      12-30-2003
Hi there,

well, its simple if you have a clock source with atleast twice the frequency
of the desired signals. But, judging from your signal namings, you are
trying to generate one clock signal out of another with a fixed phase
difference. This naturally can't be done without a dedicated PLL, which is
again out of the scope of pure digital design... But again, schoolwork is
hard sometimes...

regards,
juza

> Hi everyone,
>
> I need to generate a square wave (CLK_OUT) which is 270 degree's out of
> phase with another square wave (CLK_IN). I guess this is a simple thing

to
> do. Can anyone recommend some simple VHDL code or a state machine to do
> such a thing?
>
> Thanks in advance,
>
>
>



 
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