How do we make an IP core????

Hi every body,
I have a question that is making a strong head each to me
When you work with some EDA, like say active-HDL, you can use the
coregen to design graphicly the entity you want to use. I wonder how
this coregen is writed?
I saw some tricks in the web, where the coregen was writen in some
high level languages like Visual Basic or visual C++, and whan you
give the specification of the bloc you want it generate the VHDL code
with some printf() functions in différent files. Is some one knows how
that is done in the EDA????
I want to use the same because i have a highly parametrized
design where i have to do so much calculus over n*n matrix to identify
the structur of my design. For example, each line of my matrix describ
a FIFO and the maximum in the line describe the depth of the FIFO. and
it's the simplest calcul i have to do.
Thanks for or the helps

Ouadid

Ouadid wrote:

> I saw some tricks in the web, where the coregen was writen in some
> high level languages like Visual Basic or visual C++, and whan you
> give the specification of the bloc you want it generate the VHDL code
> with some printf() functions in différent files.

Consider learning VHDL and writing
your own code directly, for synthesis.

-- Mike Treseler

Mike Treseler

Dear Mike,
I'm not interesting in using an IP core in my design. In the fact,
i wrote my own VHDL code for an ECC codec that is defined for a
specific code. The all is working well and the synthesis is ok. The
second stage in my project is to build a coregen in order to generat
the VHDL code for any kind of this codec familly.
What i'm asking for is the way we write such a tool. In C/C++, VB,
TCL/TK????
Thanks for your suggestion.

Ouadid

Ouadid wrote:

> Dear Mike,
> I'm not interesting in using an IP core in my design. In the fact,
> i wrote my own VHDL code for an ECC codec that is defined for a
> specific code. The all is working well and the synthesis is ok. The
> second stage in my project is to build a coregen in order to generat
> the VHDL code for any kind of this codec familly.

Synthesizable cores are more valuable than vendor-specific
netlists. Consider adding parameters to your design
right in your VHDL code. You can use generic constants
for vector widths and operation modes.
Synthesis will not waste any gates on the unused modes.

-- Mike Treseler

Mike Treseler

> What i'm asking for is the way we write such a tool. In C/C++, VB,
> TCL/TK????

What you need is window with entry boxes for the programmable parameters,
which you can write in Tcl/Tk very quickly. Besides, your coregen tool will
work on any OS that Tcl/Tk supports.

Jim Wu
(remove capital letters)
http://www.geocities.com/jimwu88/chips

Jim Wu

Thanks Jim,
I think that all the EDA tools are supporting the tcl/tk language???
And do you write your coregen in order that you write the core in vhdl
with some fprintf() functions? or can we manage to write it in another
way??? My ask this in order to know how to preserve the secret of my
implantetion and the algorithm.
Thanks for the help

ouadid@iquebec.com