Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Verilog / VHDL

Reply
Thread Tools

Verilog / VHDL

 
 
EdwardH
Guest
Posts: n/a
 
      12-18-2003
Hi

I am an experienced Verilog designer and am about to start
work with a company that uses VHDL. I have been studying VHDL
and am starting to get a feel for the language. It would be good however to
be able to relate features of Verilog with equivalents in VHDL.

A specific question relates to compiler directives and command
line arguments in Verilog i.e. 'ifdef and +define+
The application is for a testbench where I want to write code to print
specific information for debug which I don't want to be printed
when the testbench executes normally. e.g. in Verilog I can write
code such as:

'ifdef debug_mode
code to print lots of debug information
'endif

There can be many of these code segments throughout the testbench
and if I want to turn them on, in the compile script I would have:

+define+debug_mode

Is there an equivalent mechanism in VHDL?

Does any body know of documents that discuss such language
equivalents?

Thanks in advance, Edward




 
Reply With Quote
 
 
 
 
Francisco Camarero
Guest
Posts: n/a
 
      12-18-2003
EdwardH wrote:
>
> Hi
>
> I am an experienced Verilog designer and am about to start
> work with a company that uses VHDL. I have been studying VHDL
> and am starting to get a feel for the language. It would be good however to
> be able to relate features of Verilog with equivalents in VHDL.
>
> A specific question relates to compiler directives and command
> line arguments in Verilog i.e. 'ifdef and +define+
> The application is for a testbench where I want to write code to print
> specific information for debug which I don't want to be printed
> when the testbench executes normally. e.g. in Verilog I can write
> code such as:
>
> 'ifdef debug_mode
> code to print lots of debug information
> 'endif
>
> There can be many of these code segments throughout the testbench
> and if I want to turn them on, in the compile script I would have:
>
> +define+debug_mode
>
> Is there an equivalent mechanism in VHDL?
>
> Does any body know of documents that discuss such language
> equivalents?
>
> Thanks in advance, Edward


I would do a similar thing using generics,
as in this very reduced example:


entity test is

generic (debug : boolean := false); -- default

end test;

architecture single of test is

begin

single : process

begin

assert not(debug)
report "Debug Message"
severity note;

wait ; -- halt;

end process;

end single;

And then, overriding the value for the generic
when necessary, e.g for ModelSim:

vsim -Gdebug=true work.test

HTH,
Fran.
 
Reply With Quote
 
 
 
 
Kai Harrekilde-Petersen
Guest
Posts: n/a
 
      12-18-2003
Francisco Camarero <"camarero a"@t ee [d.ot] ethz [do.t] ch> writes:

> EdwardH wrote:

[How to do the equivalent of '+define+debug_mode' in VHDL]:
> > There can be many of these code segments throughout the testbench
> > and if I want to turn them on, in the compile script I would have:
> >
> > +define+debug_mode
> >
> > Is there an equivalent mechanism in VHDL?
> >
> > Does any body know of documents that discuss such language
> > equivalents?

>
> I would do a similar thing using generics,
> as in this very reduced example:


[snip example]

Another approach is to have a signal on the top level of your
testbench, which you manipulate using Tcl (e.g. "force -deposit
/debug_mode true").

Or even have a (text) file parser in VHDL directly, which assigns a
value to the signal in question, based on keywords in the text file.

Regards,


Kai
 
Reply With Quote
 
Slawek Grabowski
Guest
Posts: n/a
 
      12-22-2003
Hi,
I use frequently the if-generate construct:

architecture HelloWorld of HelloWorld is
constant DEBUG : BOOLEAN := TRUE;
begin

GEN1:
if(DEBUG=TRUE) generate
assert (A=B) report "Error: It is not equal.";
end generate;

end HelloWorld;

Best Regards,
Slawek Grabowski

"Kai Harrekilde-Petersen" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> Francisco Camarero <"camarero a"@t ee [d.ot] ethz [do.t] ch> writes:
>
> > EdwardH wrote:

> [How to do the equivalent of '+define+debug_mode' in VHDL]:
> > > There can be many of these code segments throughout the testbench
> > > and if I want to turn them on, in the compile script I would have:
> > >
> > > +define+debug_mode
> > >
> > > Is there an equivalent mechanism in VHDL?
> > >
> > > Does any body know of documents that discuss such language
> > > equivalents?

> >
> > I would do a similar thing using generics,
> > as in this very reduced example:

>
> [snip example]
>
> Another approach is to have a signal on the top level of your
> testbench, which you manipulate using Tcl (e.g. "force -deposit
> /debug_mode true").
>
> Or even have a (text) file parser in VHDL directly, which assigns a
> value to the signal in question, based on keywords in the text file.
>
> Regards,
>
>
> Kai



 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
VHDL-2002 vs VHDL-93 vs VHDL-87? afd VHDL 1 03-23-2007 09:33 AM
Verilog/VHDL Simulation Elf VHDL 1 10-10-2003 04:31 PM
dummy projects in VHDL/Verilog shumon VHDL 1 09-24-2003 01:41 AM
how to design this datapath unit for DSP using VHDL/Verilog? walala VHDL 3 08-30-2003 05:26 PM
where to find DCT/IDCT for JPEG/JPEG2000 VHDL/VERILOG source code? walala VHDL 0 08-01-2003 09:44 PM



Advertisments