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Declaring ports with a complicated array type

 
 
Marius Vollmer
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      12-09-2003
Hi,

I would like to declare an entity that has a port with type

array (1 to columns) of signed (width-1 downto 0)

where both "columns" and "width" are generics of the entity. How can
I do that?

The natural (for me at least) formulation would be along the lines of

entity matrix_source is

generic (
filename : string;
rows, columns : integer;
row_delay, column_delay : integer;
zero_rows : integer;
width : integer);

subtype value is signed (width-1 downto 0);
type value_vector is array (natural range <>) of value;

port (
clk : in std_logic;
rst : in std_logic;
data : out value_vector (1 to columns));

end matrix_source;

However, this is not legal VHDL since ports can not follow entity
declarative items such as the type declarations.

I would be happy to put "value" and "value_vector" into a package but
I can't since "width" is a generic and unknown to that package.

I tried to use a multi-dimensional unconstrained array such as

type signed_vector is array (natural range <>, natural range <>)
of std_logic;

and used it as

port (
data : out signed_vector (1 to columns, width-1 downto 0));

but that is unnatural (to me) since you than need to write stuff like

data (col, width-1 downto 0) <= to_signed (..., width);

which is not only unnatural but also illegal VHDL since you can't
slice a multi-dimensional array.

I must be missing something...

Thanks in advance!

--
Marius Vollmer AG Datentechnik / E-Technik
Tel: +49-231-755-3036 Universitšt Dortmund
Fax: +49-231-755-3251 Otto-Hahn-Str.4
http://www-dt.e-technik.uni-dortmund.de 44221 Dortmund, Germany
 
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Mike Treseler
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      12-09-2003
Marius Vollmer wrote:

> The natural (for me at least) formulation would be along the lines of
>
> entity matrix_source is
>
> generic (
> filename : string;
> rows, columns : integer;
> row_delay, column_delay : integer;
> zero_rows : integer;
> width : integer);
>
> subtype value is signed (width-1 downto 0);
> type value_vector is array (natural range <>) of value;
>
> port (
> clk : in std_logic;
> rst : in std_logic;
> data : out value_vector (1 to columns));


If this is for synthesis, consider saving
the data structures for internal variables
and keep the entity ports simple.

If this is for simulation, consider
not using an entity interface at all.


-- Mike Treseler

 
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Marius Vollmer
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      12-09-2003
Mike Treseler <(E-Mail Removed)> writes:

> Marius Vollmer wrote:
>
>> The natural (for me at least) formulation would be along the lines of
>> entity matrix_source is
>> generic (
>> filename : string;
>> rows, columns : integer;
>> row_delay, column_delay : integer;
>> zero_rows : integer;
>> width : integer);
>> subtype value is signed (width-1 downto 0);
>> type value_vector is array (natural range <>) of value;
>> port (
>> clk : in std_logic;
>> rst : in std_logic;
>> data : out value_vector (1 to columns));

>
> If this is for synthesis, consider saving
> the data structures for internal variables
> and keep the entity ports simple.
>
> If this is for simulation, consider
> not using an entity interface at all.


Thanks for your answer.

The entity is for providing test data to a synthesized circuit during
simulation. So it's both for simulation _and_ for synthesis.

I have now put all types in a package, fixing the value of "width"
over all "matrix_sources", but it still is annoying that VHDL doesn't
seem to allow the construction above, for syntax reasons.
 
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Mike Treseler
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      12-09-2003
Marius Vollmer wrote:

> The entity is for providing test data to a synthesized circuit during
> simulation. So it's both for simulation _and_ for synthesis.
>
> I have now put all types in a package, fixing the value of "width"
> over all "matrix_sources"


Glad you got it working.

> but it still is annoying that VHDL doesn't
> seem to allow the construction above, for syntax reasons.


That is one reason why it is standard practice
*not* to instance the testbench, but to drive test data
directly from signals in the architecture of
a null entity.

-- Mike Treseler

 
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Jim Lewis
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      12-10-2003

The VHDL-200X Fast-Track is considering the following extensions:
type std_logic_matrix is array (natural range<>) of std_logic_vector;

Then you could declare a signal or port as follows:
signal A : std_logic_matrix(7 downto 0)(5 downto 0) ;

Similarly, a subtype declaration:
subtype Matrix_5x5 is std_logic_matrix(4 downto 0)(4 downto 0) ;

The intent then would be that these get added to the
standard packages (1164 and numeric_std).

There are additional proposals. You can find information about
vhdl-200x at: http://www.eda.org/vhdl-200x/
vhdl-200x fast track: http://www.eda.org/vhdl-200x/vhdl-200x-ft

There is a link to the proposals, meeting notes, and the
reflector at each of the above webpages.


Cheers,
Jim
P.S.
IEEE standards policies and procedures require that anyone that
has a vested in a standard be able to attend meetings and comment
on the working groups work (meaning: although we encourage
people to join IEEE and DASC, non-members are permitted
to join reflector - even do work).
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~


Mike Treseler wrote:

> Marius Vollmer wrote:
>
>> The entity is for providing test data to a synthesized circuit during
>> simulation. So it's both for simulation _and_ for synthesis.
>>
>> I have now put all types in a package, fixing the value of "width"
>> over all "matrix_sources"

>
>
> Glad you got it working.
>
>> but it still is annoying that VHDL doesn't
>> seem to allow the construction above, for syntax reasons.

>
>
> That is one reason why it is standard practice
> *not* to instance the testbench, but to drive test data
> directly from signals in the architecture of
> a null entity.
>
> -- Mike Treseler


 
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Marius Vollmer
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      12-10-2003
Jim Lewis <(E-Mail Removed)> writes:

> The VHDL-200X Fast-Track is considering the following extensions:
> type std_logic_matrix is array (natural range<>) of std_logic_vector;


They will also need to change VHDL itself to allow unconstrained
arrays as elements of arrays, right? (Just to check my
understanding.)
 
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Jim Lewis
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      12-10-2003
Correct.

Marius Vollmer wrote:

> Jim Lewis <(E-Mail Removed)> writes:
>
>
>>The VHDL-200X Fast-Track is considering the following extensions:
>> type std_logic_matrix is array (natural range<>) of std_logic_vector;

>
>
> They will also need to change VHDL itself to allow unconstrained
> arrays as elements of arrays, right? (Just to check my
> understanding.)


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

 
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