special FIFO

Hello!

I want to build a FIFO for a special purpose:
I've got a microcontroller that interfaces to a SDRAM via an
SDRAM-interface. The microcontrollers data width is 16 bit while the
SDRAM-interface needs 32 bit (if i write something to the sdram, in the
first clock cycle, the interface needs the bank, row and column address (32
bit) and in the second clock cycle the data (only 16 bit, the upper 16bit
are just don't care)).
Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is
not important, only the 2 words of 32 bit have to be sent one clock cycle
after the other. (so i don't need a "doubling" of the clock rate, just a
method to combine the two incoming words) could it work with a kind of shift
register?

Thank you for your help!

Simone

Simone Winkler

take two 16 bit fifo's stack them on top of each other and mux in your data
to each one using a T flop as a select/ff enable.


"Simone Winkler" <> wrote in message
news:...
> Hello!
>
> I want to build a FIFO for a special purpose:
> I've got a microcontroller that interfaces to a SDRAM via an
> SDRAM-interface. The microcontrollers data width is 16 bit while the
> SDRAM-interface needs 32 bit (if i write something to the sdram, in the
> first clock cycle, the interface needs the bank, row and column address
(32
> bit) and in the second clock cycle the data (only 16 bit, the upper 16bit
> are just don't care)).
> Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is
> not important, only the 2 words of 32 bit have to be sent one clock cycle
> after the other. (so i don't need a "doubling" of the clock rate, just a
> method to combine the two incoming words) could it work with a kind of
shift
> register?
>
> Thank you for your help!
>
> Simone
>
>

NJ

> > Now I need a FIFO that converts the 2x16 bit to one 32-bit word. Timing is
> > not important, only the 2 words of 32 bit have to be sent one clock cycle
> > after the other. (so i don't need a "doubling" of the clock rate, just a
> > method to combine the two incoming words) could it work with a kind of
> shift register?

Hi,

You may wish to consider making an arbiter (a type of FSM) that would
acquire two 16 bit words, then write them to the SDRAM when an entire
32-bit word is complete. This is a fairly simple FSM: Wait for
word1, store word1 to upper half of 32 bit word, wait for word 2,
store to lower half of 32 bit output, produce output, go idle. The
idea can be expanded to handle multiple ports and higher rate
dataflows.

As you mentioned, as long as the 16 data is being generated slower
than you store it, you may not need a FIFO. Or, if you have some sort
of flow-control, you would not need a FIFO. Note that SDRAM
controllers may allow 12-15 clocks between read or write operations,
so you're probably okay unless you are in a burst situation.

Bryce

Bryce