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VHDL - How do I model a 6T SRAM cell in VHDL |
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12-05-2003, 07:53 PM
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#1 |
How do I model a 6T SRAM cell in VHDL
Does nay one know how to model a signle-port 6t SRAM cell in VHDL? You
need to differentiate between the read and the write. KM |
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12-05-2003, 08:30 PM
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#2 |
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Posts: n/a
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Re: How do I model a 6T SRAM cell in VHDL
KM wrote:
> Does nay one know how to model a signle-port 6t SRAM cell in VHDL? You > need to differentiate between the read and the write. http://vlsi.wpi.edu/aries/5.html#5.3 http://members.aol.com/vhdlcohen/vhdl/Models.html -- Mike Treseler Mike Treseler |
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