N_bit decoder/encoder

How can I implement N-bit decoder (encoder?) (I mean 001 => 00000001, 010 =>
00000010, 011 => 00000100, 111 => 10000000...), where N is a parameter?
It's quite easy with integer signal on input but I have bit_vector.

Gietek

Have you looked into design templates? In addition, here is mine:

process
O <= (others => '0');
O(code) <= '1';
end;

valentin tihomirov

Gietek wrote:
> How can I implement N-bit decoder (encoder?) (I mean 001 => 00000001, 010 =>
> 00000010, 011 => 00000100, 111 => 10000000...), where N is a parameter?
> It's quite easy with integer signal on input but I have bit_vector.
>
>
try an recursive approach with generate-statements.

dec(1) ~ feed trough / inverter
dec(n) ~ dec(n/2) + ...

j

Joerg Ritter

Joerg Ritter a écrit:
> Gietek wrote:
>
>> How can I implement N-bit decoder (encoder?) (I mean 001 => 00000001,
>> 010 =>
>> 00000010, 011 => 00000100, 111 => 10000000...), where N is a parameter?
>> It's quite easy with integer signal on input but I have bit_vector.
>>
>>
> try an recursive approach with generate-statements.
>
> dec(1) ~ feed trough / inverter
> dec(n) ~ dec(n/2) + ...
>
> j
>

....
nn : in std_logic_vector(a downto 0); -- a = log2(n)
output : out std_logic_vector(n downto 0);
....
output <= ((to_integer(unsigned(nn)) => '1', others => '0');
....

(quite similar to V. Tihomirov's approach )

Nicolas

Nicolas Matringe

"Gietek" <> wrote in message news:<bqlpmc$fvu$>...
> How can I implement N-bit decoder (encoder?) (I mean 001 => 00000001, 010 =>
> 00000010, 011 => 00000100, 111 => 10000000...), where N is a parameter?
> It's quite easy with integer signal on input but I have bit_vector.

Here is something close to what you want, I think. It using
std_logic_vector inputs, not bit_vector, but it should be easy to
adapt it for your needs. The output codes are arbitrary and not the
ones you want--again easily changed.

--================================================== ============================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
--================================================== ============================
ENTITY LookUp IS
GENERIC ( addr_width : natural := 3;
tout_width : natural := 12 );
PORT ( addr : in std_logic_vector( addr_width - 1 downto 0 );
tout : out std_logic_vector( tout_width - 1 downto 0
));
END LookUp;

ARCHITECTURE archlookup OF lookup IS


subtype tablerng is natural range 0 to 2**addr_width - 1;
type ttable is array( tablerng ) of std_logic_vector( tout_width -
1 downto 0 );

constant table : ttable := ( "000000100000", --0
"000000100001", --1
"000000100010", --2
"000000100011", --3
"000000100100", --4
"000000100101", --5
"000000100110", --6
"000000100111" ); --7


BEGIN

tout <= table( to_integer( unsigned( addr ) ) );

END archlookup;

Charles M. Elias