choice in a case satement

Hello all,

I wondered if you could give me some insight into
why the choices of a case statement must be
locally static i.e. it can't be a generic value.

Is there some workaround to still be able to
generically specify the binary values of the
states of my state machine (eg. to chosse a one-hot
state machine when I implement the component)

:My symphony compiler complains about this.

--
JB Viviers

jan

>I wondered if you could give me some insight into
>why the choices of a case statement must be
>locally static i.e. it can't be a generic value.
>
>Is there some workaround to still be able to
>generically specify the binary values of the
>states of my state machine (eg. to chosse a one-hot
>state machine when I implement the component)
>

Case choice must be locally static to protect the code from
illegal choices. If the choice was globally static, then errors could occur.
For example, assume a generic g of value 4, and a signal S declared as:
signal S : std_logic_vector(g-1 downto 0);
...
case S is
when "0000" => ...
when "0001" => ...
when others => ...
end case

Now in the component instantiation or in a configuration, I set g to 32.
The case choices are no longer valid.
In a way, it protects the user from making dumb mistakes.
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

VhdlCohen

jan a écrit:
> Hello all,
>
> I wondered if you could give me some insight into
> why the choices of a case statement must be
> locally static i.e. it can't be a generic value.
>
> Is there some workaround to still be able to
> generically specify the binary values of the
> states of my state machine (eg. to chosse a one-hot
> state machine when I implement the component)

Hi
In the case of the state machine encoding, use an enumerated type for
your state vector and then either let your synthesizer choose the
encoding scheme or add some synthesis directives or attributes to
specify the encoding scheme:

type T_STATE is (IDLE, VALID, READ);
signal STATE : T_STATE;

attribute ENUM_ENCODING : string; -- attribute declaration
attribute ENUM_ENCODING of T_STATE : type is “100 010 001”;

Nicolas

Nicolas Matringe