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VHDL - Looking for a VHDL or Verilog RAM Model that modles Common RAM Faults |
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11-26-2003, 07:50 PM
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Looking for a VHDL or Verilog RAM Model that modles Common RAM Faults
Dear Gentle Persons,
Does anyone know where I could get a Verilog or VHDL RAM Model that models common RAM Faults like Stuck At Faults on the Address, Data Lines, Stuck Ram Cells, Coupling faults Etc? I would also be interested in Verilog or VHDL implementation of a March SS RAM Test, or any March type RAM Test. Robert Posey Robert Posey |
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