How to design a 16 bit CISC processor ?

I'm student of Univeristy of Technology in Poland
My task is to design a 16 bit CISC processor in VHDL or Verilog language
I know how to do this in theory but it is a black magic form me to create it
in VHDL or Verilog
I know basics of ModelSim VHDL
I created some simple hardware parts
Does anyone know a site where I can find help
or somebody maybe will give me some instructions

// Helpless Student

YacentY

YacentY wrote:
> I'm student of Univeristy of Technology in Poland
> My task is to design a 16 bit CISC processor in VHDL or Verilog language
> I know how to do this in theory but it is a black magic form me to create it
> in VHDL or Verilog
> I know basics of ModelSim VHDL
> I created some simple hardware parts
> Does anyone know a site where I can find help
> or somebody maybe will give me some instructions
>
> // Helpless Student

I suggest you either get this project
changed to something that interests you
or drop the class. The world doesn't need
any more bad CPU cores or helpless engineers.


-- Mike Treseler

Mike Treseler

YacentY wrote:

> I'm student of Univeristy of Technology in Poland
> My task is to design a 16 bit CISC processor in VHDL or Verilog language

Isn't it a little bit tough for a class project?
(I took 6 Months (8h/day) for a 16 Bit RISC core with known instruction
set and the solution was not really satisfiying.)


> I know how to do this in theory but it is a black magic form me to create it
> in VHDL or Verilog

First of all: Think about the instruction set.
Then: Think about a data path, that fits to the instruction set.
Think about how to compute every instruction on the chosen data path.
(Think about state machines and register-transfer-lists.)


> I know basics of ModelSim VHDL
> I created some simple hardware parts

If you know, what you have to model (an ALU, a bus system, the
registers, the main state machine ....) it is relatively easy to have
the idea how to implement in an a HDL. (Many problems will occur and the
final description is not easy, but the idea what a component can be in
real hardware is relatively easy.)



Ralf

Ralf Hildebrandt

Take a look at the www.opencores.org However, your task seems to be too
complex for your level....

/Mikhail


"YacentY" <> wrote in message
news:3fc4ffdd$...
> I'm student of Univeristy of Technology in Poland
> My task is to design a 16 bit CISC processor in VHDL or Verilog language
> I know how to do this in theory but it is a black magic form me to create
it
> in VHDL or Verilog
> I know basics of ModelSim VHDL
> I created some simple hardware parts
> Does anyone know a site where I can find help
> or somebody maybe will give me some instructions
>
> // Helpless Student
>
>
>

MM

"Mike Treseler" <> wrote in message
news:...
>
> I suggest you either get this project
> changed to something that interests you
> or drop the class. The world doesn't need
> any more bad CPU cores or helpless engineers.
>
>
> -- Mike Treseler
>

Mike,

Are you having a bad day ? ) Take it easy...

/Mikhail

MM

> I'm student of Univeristy of Technology in Poland
> My task is to design a 16 bit CISC processor in VHDL or Verilog language
> I know how to do this in theory but it is a black magic form me to create
it
> in VHDL or Verilog
> I know basics of ModelSim VHDL
> I created some simple hardware parts
> Does anyone know a site where I can find help
> or somebody maybe will give me some instructions
>
> // Helpless Student
today I was talking with my professor and he said that I had to simulate
only my processor.
I've done instruction set, I thought about architecture so I think
theoretical i have that processor how can I do it in verilog or VHDL?? which
one will be easiest??

YacentY

If You only need to simulate the porcessor, then You can take a look
at the FMF model library
www.eda.org/fmf
Look for processor models. There are some VHDL VITAL models that You
may be able to use.

p89c51 for examp...

http://www.eda.org/fmf/fmf_public_models/proc/

"YacentY" <> wrote in message news:<>...
> > I'm student of Univeristy of Technology in Poland
> > My task is to design a 16 bit CISC processor in VHDL or Verilog language
> > I know how to do this in theory but it is a black magic form me to create
> it
> > in VHDL or Verilog
> > I know basics of ModelSim VHDL
> > I created some simple hardware parts
> > Does anyone know a site where I can find help
> > or somebody maybe will give me some instructions
> >
> > // Helpless Student
> today I was talking with my professor and he said that I had to simulate
> only my processor.
> I've done instruction set, I thought about architecture so I think
> theoretical i have that processor how can I do it in verilog or VHDL?? which
> one will be easiest??

Milos

YacentY wrote:

> today I was talking with my professor and he said that I had to simulate
> only my processor.

Umm .. well if I mix up the words, I get:

"..he said, that I only had to simulate my processor"

(Could it be a translation mistake? Otherwise Your task would not be
"smaller" than before.)

It makes a big difference if you only have to simulate it or have to
model it synthesizable.


> I've done instruction set, I thought about architecture so I think
> theoretical i have that processor how can I do it in verilog or VHDL??

Split all into pieces. (It's like a house, that is build of many pieces.)

Describe these pieces (components). Connect the pieces to bigger blocks.


> which one will be easiest??

It does not matter if you chose Verilog or VHDL. Some people like
Verilog more, some VHDL. (I for myself prefer VHDL.)
Nevertheless ... all can be written in both languages.

For any HDL it is highlig recommended to read a beginners book. "HDL
chip design" ( http://www.doone.com/hdl_chip_des.html ) was very helpful
for me. I covers every example in Verilog in VHDL (if possible).

Ralf

Ralf Hildebrandt

"YacentY" <> wrote:

Myself, I can only say this:

http://www.pjrc.com/tech/osu8/index.html

This is the best webpage on microprocessor design I have managed to
find over a very long period of time. Make most of it.

T.

A. Tomaszewski

Mike Treseler <> wrote in message news:<>...
> YacentY wrote:
> > I'm student of Univeristy of Technology in Poland
> > My task is to design a 16 bit CISC processor in VHDL or Verilog language
> > I know how to do this in theory but it is a black magic form me to create it
> > in VHDL or Verilog
> > I know basics of ModelSim VHDL
> > I created some simple hardware parts
> > Does anyone know a site where I can find help
> > or somebody maybe will give me some instructions
> >
> > // Helpless Student
>
> I suggest you either get this project
> changed to something that interests you
> or drop the class. The world doesn't need
> any more bad CPU cores or helpless engineers.
>
>
> -- Mike Treseler

Sure boss.

Andrew

A. Tomaszewski