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VHDL - Type Conversion in Procedure Call |
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#1 |
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Hi,
I want to include a type conversion in a procedure interface list as shown below. The procedure "proc" operates on integer formals (a, b and c) while the process contains real actuals (a1, b1 and c1). The procedure call contains type conversion in the association list. entity test2 is port (et1 : inout bit); end entity test2; architecture tarch of test2 is procedure proc (variable a , b : in integer; variable c : out integer) is begin c := a + b; end procedure proc; begin testp : process is variable a1, b1, c1 : real; begin proc (a => integer(a1), b => integer(b1), real(c) => c1);--**Type Con end process testp; end architecture tarch; Is it legal to include a type conversion as shown above in a procedure call? The compiler returns an error: actual associated with variable parameter must be a variable for the associations : a => integer(a1), b => integer(b1) What the error mean and why is it being reported? Thanks, Anand Anand P Paralkar |
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#2 |
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Posts: n/a
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Anand P Paralkar wrote:
[snip] > procedure proc (variable a , b : in integer; > variable c : out integer) is [snip] > proc (a => integer(a1), b => integer(b1), real(c) => c1);--**Type Con [snip] >The compiler returns an error: > > actual associated with variable parameter must be a variable > > for the associations : > > a => integer(a1), b => integer(b1) > > What the error mean and why is it being reported? It means that the item on the right hand side of the of the => must be a variable. The object returned by a function is a constant, not a variable. The reason why it must be a variable is because you said so! However, I think you meant constant, because the mode of formals a and b is IN. So your procedure declaration should be: procedure proc (constant a , b : in integer; variable c : out integer) is Or even simpler (my preference): procedure proc (a , b : in integer; c : out integer) is If the object class for a parameter of mode in is not specified, constant is assumed. If the object class for a parameter of mode out or inout is not specified, variable is assumed. As said, normally I do not specify the object class, unless signal or file is needed. Paul. Paul Uiterlinden |
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#3 |
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Posts: n/a
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Anand,
> What the error mean and why is it being reported? > actual associated with variable parameter must be a variable I think the error message is misleading. I think it should have said that variables are not permitted as a formal input to a subprogram I have looked through the LRM, for functions, all formal parameters are of mode in and the object class must be constant, signal, or file (clause 2.1.1). I could not find an explicit statement for procedures, but my bet would be that this restriction also applies to procedure inputs. Anyone know an LRM reference? From a methodology point of view, even if variables were allowed as inputs, I would never recommend them. Constant class inputs are allowed to be associated with a value from an expression (a variable name is a simple expression), while variable class objects must be associated with a variable object. Hence, applying a variable class to an input limits the usability of the procedure. This is the only thing I see problematic with your code. So, I reach the same conclusion that Paul U. did, your procedure declaration should be either: procedure proc (constant a , b : in integer; variable c : out integer) is Or (since constant is the default in and variable is the default out): procedure proc (a , b : in integer; c : out integer) is Or (since "in" is the default mode): procedure proc (a , b : integer; c : out integer) is For readability, I like the first one best. These are the simplified rules I use for procedure IO: In: constant everything except objects that must be signal signal Objects that use a signal attribute (such as 'event) Objects in a wait statement (not recommended for synthesis) Testbench: Objects from design under test (otherwise they may not be updated) Out, InOut: variable Things that go to a process (such as an error count) signal If procedure called concurrently (such as in synthesis) Testbench: Objects to the design under test Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~ Jim Lewis Director of Training private.php?do=newpm&u= SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~ Anand P Paralkar wrote: > Hi, > > I want to include a type conversion in a procedure interface list as shown > below. > > The procedure "proc" operates on integer formals (a, b and c) while the > process contains real actuals (a1, b1 and c1). > > The procedure call contains type conversion in the association list. > > entity test2 is > port (et1 : inout bit); > end entity test2; > > architecture tarch of test2 is > procedure proc (variable a , b : in integer; > variable c : out integer) is > begin > c := a + b; > end procedure proc; > begin > > testp : process is > variable a1, b1, c1 : real; > begin > proc (a => integer(a1), b => integer(b1), real(c) => c1);--**Type Con > end process testp; > end architecture tarch; > > Is it legal to include a type conversion as shown above in a procedure > call? The compiler returns an error: > > actual associated with variable parameter must be a variable > > for the associations : > > a => integer(a1), b => integer(b1) > > What the error mean and why is it being reported? > > Thanks, > Anand > Jim Lewis |
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