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I use Xilinx ISE webpack 6.1 sp 2, and a spartanII/e xc2s50e.

In my project I use the signals clk_in and clk_out.
The frequency of clk_out can be half of clk_in one, or can be equal to
clk_in.
clk_out is the "official" clock that goes to the rest of fpga.

Now I use clk_out = clk_in/2, and I placed clk_in in GCLK pin using
constrain.

I wrote:
clk_out <= clk2 when reset = '0' else '0';

gen_clk: process(clk_in)
begin
if rising_edge(clk_in) then
clk2 <= not clk2;
end if;
end process;

(clk2 is a simple signal) in this way all works.

If I try to make clk_out equal to clk_in I obtain this error:
ERRORack:1107 - Unable to combine the following symbols into a single
IOB component:
PAD symbol "clk_in" (Pad Signal = clk_in)
BUF symbol "clk_in_IBUF" (Output Signal = clk_in_IBUF)
Each of the following constraints specifies an illegal physical site
for a component of type IOB:
Symbol "clk_in" (LOC=B
Please correct the constraints accordingly.

I cannot understand....

How can I avoid this error without moving clk_in pin from GCLK?

thanks

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