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VHDL/Verilog simulation problem

 
 
Andy Botterill
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Posts: n/a
 
      11-04-2003
I am trying to do a simulation that has the design described in verilog
and the testbench in VHDL. The simulation compiles and works OK in
ModelSim but gives me problems with Aldec Active-HDL.

Entity "testbench" has been skipped - no difference detected.
Compile Architecture "rtl_not_tb" of Entity "testbench"
Error: ELAB1_0002: The ITF file has an invalide format.
Warning: ELAB1_0026: rtl_not_tb.vhd : (43, 0): There is no default
binding for component "rtl_not".(No entity named "rtl_not" was found).
Top-Level unit detected
Entity => testbench
Compile failure 1 Errors 1 Warnings Analysis time : 0.3 [s]

The VHDL testbench is like this :-

-- ModelSim
library ieee;
use ieee.std_logic_1164.all;

entity testbench is
port(
F: out std_logic;
A: in std_logic
);
end;

--- architecture TB_ARCHITECTURE of rtl_not_tb is
architecture rtl_not_tb of testbench is

component rtl_not
port(
F: out std_logic;
A: in std_logic
);
end component;

signal IN_A : std_logic := '0';

signal OUT_F : std_logic;

begin
stimulus:
process begin
IN_A <= '0'; wait for 100 ns;
IN_A <= '1'; wait for 100 ns;
IN_A <= '0'; wait for 100 ns;
IN_A <= '1'; wait for 100 ns;
IN_A <= '0'; wait for 100 ns;
IN_A <= '1'; wait for 100 ns;
IN_A <= '0'; wait for 100 ns;
IN_A <= '1'; wait for 100 ns;
IN_A <= '0'; wait for 100 ns;
IN_A <= '1'; wait for 100 ns;

wait;
end process;

m: rtl_not port map( F=>OUT_F , A=>IN_A );

end;

The verilog design is like this :-

`define PERIOD 100

module rtl_not( F , A);
output F;
input A;

assign F = ~A;

endmodule

I am novice at VHDL and would appreciate someone giving some ideas as to
what to check. Many thanks in advance.

[ Test engineer trying to understand more about design. ]




--
Andy Botterill
 
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