>Subject: algorithm problem

>From: "Adam" http://www.velocityreviews.com/forums/(E-Mail Removed)

>Date: 11/2/03 8:45 PM US

>Message-id: <lbkpb.3423$(E-Mail Removed)>

>

>Hello,

>

> I'm trying to code a module to do the >following algorithm:

>

>If Input is even, divide by 2 and do two's >complement(invert bits and add 1)

>If Input is odd, increment by 1 and then >divide by 2.
You might want to look at the following code.

library ieee;

use ieee.std_logic_1164.all;

---

---

---

---

entity mystery is

generic

(

length: integer := 4

);

port --- bit zero is lsb, dividing means shifting right

(

inputs: in std_logic_vector(length-1 downto 0);

outputs: out std_logic_vector(length-1 downto 0)

);

end entity mystery;

---

---

---

---

architecture mystery of mystery is

---

function increment(vektor: std_logic_vector)

return std_logic_vector is

variable result: std_logic_vector(vektor'range);

variable carry: std_logic;

begin

carry := '1';

for count in vektor'low to vektor'high loop

result(count) := vektor(count) xor carry;

carry := vektor(count) and carry;

end loop;

return (result);

end function increment;

---

begin

mysterious: process(inputs)

variable zwischen_even: std_logic_vector(length-1 downto 0);

variable zwischen_odd: std_logic_vector(length-1 downto 0);

begin

if (inputs(0) = '0') then

zwischen_even := not ('0' & inputs(length-1 downto 1));

outputs <= increment(zwischen_even);

else

zwischen_odd := increment(inputs);

outputs <= '0' & zwischen_odd(length-1 downto 1);

end if;

end process mysterious;

end architecture mystery;