Velocity Reviews > VHDL > Compare pairs of bits between two slv's ?

# Compare pairs of bits between two slv's ?

Tony Benham
Guest
Posts: n/a

 10-31-2003
I've been puzzling how I can write concise vhdl that will basically set a
bit if any pair of bits in two slv's are both hi ?
A sort of pseudo code for what I want to do is as follows
mask : std_logic_vector(7 downto 0) ;
trig : std_logic_vector(7 downto 0) ;
set : std_logic;

set <= '0' ;
for i in 0 to 7
If mask(i) AND trig(i) = '1'
set <= '1' ;
end if ;
end for ;

In english, if any pair of bits in the two slv's are both hi, the set will
be set to one, else zero

I thought about using For-Generate, but I'm puzzled how to apply for this
case ?

Regards
Tony

Valentin Tihomirov
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Posts: n/a

 10-31-2003
S1 <= '0' when (Mask and Trig) = 0 else '1';

David Bishop
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Posts: n/a

 11-01-2003

This is why we are thinking of putting vector reduction into
VHDL.

Try this:

set := or_reduce (mask and trig);

You will find a copy of "or_reduce" at:
http://www.vhdl.org/vhdlsynth/

This is functionality we also plan to add in 1164 as well.

Tony Benham wrote:

> I've been puzzling how I can write concise vhdl that will basically set a
> bit if any pair of bits in two slv's are both hi ?
> A sort of pseudo code for what I want to do is as follows
> mask : std_logic_vector(7 downto 0) ;
> trig : std_logic_vector(7 downto 0) ;
> set : std_logic;
>
> set <= '0' ;
> for i in 0 to 7
> If mask(i) AND trig(i) = '1'
> set <= '1' ;
> end if ;
> end for ;
>
> In english, if any pair of bits in the two slv's are both hi, the set will
> be set to one, else zero
>
> I thought about using For-Generate, but I'm puzzled how to apply for this
> case ?
>
> Regards
> Tony
>
>

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Valentin Tihomirov
Guest
Posts: n/a

 11-02-2003
I've just reading an answer to my qustion here
http://www.eda.org/comp.lang.vhdl/FAQ1.html
and encountered Reduction section.

-- this concurrent assignment performs an "or"
-- reduction on "a_vec"
a <= '0' when (a_vec = (a_vec'range => '0')) else '1';

-- while this calculates an "and" reduction
a <= '1' when (a_vec = (a_vec'range => '1')) else '0';

Read there about reducing vectors containing 'X' values.