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assignment with *when* statement

 
 
Valentin Tihomirov
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      10-29-2003
1. Why this works only in architecture body?
A <= 0 when A = 9 else A + 1;
-- and this
with A select
A <= 0 when 9,
<= (A + 1) when others;

But not in clocked process? I have to write
A <= A + 1;
if A = 9 then
A <= 0;
end if;



2. In addition, I cannot force my compiler to analyze this

signal A: std_logic;
signal I: integer;

A <= (I = 10); -- how can I convert bool into std_logic?

I have to write
A <= '1' when (I = 10) else '0';


 
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Shaomin
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      10-29-2003
Valentin Tihomirov wrote:
> 1. Why this works only in architecture body?
> A <= 0 when A = 9 else A + 1;
> -- and this
> with A select
> A <= 0 when 9,
> <= (A + 1) when others;

Above is concurrent assignment;


> But not in clocked process? I have to write
> A <= A + 1;
> if A = 9 then
> A <= 0;
> end if;

Above is sequential assignment;

>
>
> 2. In addition, I cannot force my compiler to analyze this
>
> signal A: std_logic;
> signal I: integer;
>
> A <= (I = 10); -- how can I convert bool into std_logic?
>
> I have to write
> A <= '1' when (I = 10) else '0';
>
>

You could define boolean true and false as 1 and 0

 
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Mike Treseler
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      10-29-2003
> Valentin Tihomirov wrote:

>> I have to write
>> A <= '1' when (I = 10) else '0';



signal A: std_logic;
signal I: integer;

function active_high (arg : boolean)
return std_ulogic is begin
if arg then
return '1';
else
return '0';
end if;
end function active_high;

begin

A <= active_high(I = 10);


-- Mike Treseler

 
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Valentin Tihomirov
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      10-30-2003
Isn't there such a function in a standard library/package?


 
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Valentin Tihomirov
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      10-30-2003
The assignments in architecture body are concurrent while are sequential in
a clockecd process. I just want to understand why I can use
A <= 0 when SpecialCase else A + 1;
in a concurrent assignment but cannot in a seqential assignment and have to
use if-then-else instead? The combinational logic should be the same, the
only difference is a register at ist output in a sequential assignment.


 
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Jonathan Bromley
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      10-30-2003
"Mike Treseler" <(E-Mail Removed)> wrote in
message news:(E-Mail Removed)...

> >> A <= '1' when (I = 10) else '0';


> signal A: std_logic;
> signal I: integer;
>
> function active_high (arg : boolean)
> return std_ulogic is begin
> if arg then
> return '1';
> else
> return '0';
> end if;
> end function active_high;
>
> begin
>
> A <= active_high(I = 10);


Another formulation, which I find aesthetically pleasing:

type sul_bool is array(boolean) of std_ulogic;
constant active_high: sul_bool := (
FALSE => '0' ,
TRUE => '1' );
signal A: std_logic;
signal I: integer;
begin
A <= active_high(I = 10);

Sadly you can't use a lookup-table "conversion function"
of this kind in a port map.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: http://www.velocityreviews.com/forums/(E-Mail Removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



 
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Jonathan Bromley
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      10-30-2003
"Valentin Tihomirov" <(E-Mail Removed)> wrote in
message news:bnqqj7$153sq3$(E-Mail Removed)-berlin.de...

> I just want to understand why I can use
> A <= 0 when SpecialCase else A + 1;
> in a concurrent assignment but cannot in a seqential
> assignment and have to use if-then-else instead?


It is a curiosity of the way VHDL syntax was defined.

At base, EVERYTHING in VHDL is a process - so the language
has rules that define how concurrent assignments, concurrent
procedure calls etc. can be rewritten as processes. Here
is the rewriting rule for your conditional signal assignment:

1) Write the equivalent if-then-else procedural statement:

if SpecialCase then
A <= 0;
else
A <= A + 1;
end if;

2) Determine all the signals that take part in calculation
of the right-hand-side of the assignment, and use
them to build a sensitivity-list "wait" statement:

wait on SpecialCase, A;

3) Put those two statements in a process:

process begin
if SpecialCase then
A <= 0;
else
A <= A + 1;
end if;
wait on SpecialCase, A;
end process;

So far, so good. All this is very clear. What is slightly
less clear is why you can't simply use "if" and "case"
statements as concurrent statements, instead of the curious
conditional and selected assignments. But that's the way
it was defined, so we must live with it.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: (E-Mail Removed)
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



 
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Brian Drummond
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      10-30-2003
On Thu, 30 Oct 2003 12:52:06 +0200, "Valentin Tihomirov"
<(E-Mail Removed)> wrote:

>The assignments in architecture body are concurrent while are sequential in
>a clockecd process. I just want to understand why I can use
> A <= 0 when SpecialCase else A + 1;
>in a concurrent assignment but cannot in a seqential assignment and have to
>use if-then-else instead? The combinational logic should be the same, the
>only difference is a register at ist output in a sequential assignment.
>

Probably to distinguish clearly between concurrent and sequential styles
of programming. Let the compiler catch a lot of potential errors, and
make it clear to readers which programming domain you are in.

VHDL has elements of two completely different styles of programming
language. Concurrent assignments are essentially a form of functional
programming (think SASL, Haskell, Miranda) - as an easy and natural way
of expressing parallelism, while within a process you have a (modified)
form of sequential programming, as in C or Pascal. (One obvious
modification is the deferred assignment to signals - if you need
immediate assignment, use variables instead. Again, the two assignment
symbols <= and := help keep the distinction clear)

Think of it as two separate languages in one, trying hard not to step on
each other's toes.

- Brian
 
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Valentin Tihomirov
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      10-30-2003
I understand which clauses lead to which logic (combinational or
sequential). I wanted to understand why two different clauses are used to
express the same logic? Namely, why if-then-else clause is good for
sequential while select is good for combinational? The statement

A <= 0 when SpecialCase else B + 1;

generates a MUX2 with 2 inputs:
- B + 1;
- 0;

The output of the mux is fed to signal A. Why should I use if-then-else
caluse instead to implement the same MUX when its output is fed to reg A
input?

VHDL has special expression like
if RisingEdage(CLK)
to distinguish between combinational and synchronous logic. Why to enforce
it with if-then redundancy?


 
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Allan Herriman
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      10-31-2003
On Thu, 30 Oct 2003 11:23:07 -0000, "Jonathan Bromley"
<(E-Mail Removed)> wrote:

>"Valentin Tihomirov" <(E-Mail Removed)> wrote in
>message news:bnqqj7$153sq3$(E-Mail Removed)-berlin.de...
>
>> I just want to understand why I can use
>> A <= 0 when SpecialCase else A + 1;
>> in a concurrent assignment but cannot in a seqential
>> assignment and have to use if-then-else instead?

>
>It is a curiosity of the way VHDL syntax was defined.


s/curiosity/mistake/

IMHO, this feature makes VHDL harder to learn. I imagine it also
makes it harder to parse. I believe it only exists for historical
reasons.

Most users think of a signal assignment as

target <= expression;

or a variable assignment (or constant initialisation) as

target := expression;

Easy so far, until you find out that the syntax of 'expression' varies
depending on where the assignment is taking place. Not good.

>So far, so good. All this is very clear. What is slightly
>less clear is why you can't simply use "if" and "case"
>statements as concurrent statements, instead of the curious
>conditional and selected assignments. But that's the way
>it was defined, so we must live with it.


I believe the VHDL 200x folk (the Modeling and Productivity group) are
doing something about this.

Hopefully we will be able to do this:

constant foo : integer = 7 when bar else 3;

Using the current language definition, I would need to create a
function to do the job of that simple expression.

Regards,
Allan.
 
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