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Coding an Asynchronous state machine

 
 
Jamie
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      10-20-2003
I am trying to put together a state machine that is entirely
asynchronous - NO CLK involved at all. But I just cant seem to get it
to synthesize.

I have 2 port inputs, A and B, that I want to trigger the state
transitions and outputs. The structure im trying is something like the
following:


port(OBIT: out std_logic, A: in std_logic, B: in std_logic...)

process(A, B..)
if (A='0') and (B='0') then
OBIT <= '0';
next_state <= S1;
end if;
.....
end process;
 
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Renaud Pacalet
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      10-20-2003
Jamie a écrit :
> I am trying to put together a state machine that is entirely
> asynchronous - NO CLK involved at all. But I just cant seem to get it
> to synthesize.
>


Do you have a rough idea of the kind of hardware you expect? If not, then you're
asking too much: a logic synthesizer just can't translate any VHDL description
in hardware.

> I have 2 port inputs, A and B, that I want to trigger the state
> transitions and outputs. The structure im trying is something like the
> following:
>
>
> port(OBIT: out std_logic, A: in std_logic, B: in std_logic...)
>
> process(A, B..)
> if (A='0') and (B='0') then
> OBIT <= '0';
> next_state <= S1;
> end if;
> .....
> end process;


What is your favourite asynchronous church? DI, QDI, SI, bundle data, dual rail
encoding, two phases, four phases, other? Do you know what a Muller C-element
is? Asynchronous design is something very specific, although some asynchronous
priests pretend that synchronous design is just a sub-case of the much more
general asynchronous design. You can't use the classical synchronous flow (VHDL
+ logic synthesizer) without any modification. Google will give you some
pointers on using synchronous languages and CAD tools for asynchronous design
(one key name: Daniel H. Linder) but you'll need, at least, a specific standard
cells library... You can search for specific tools too (TAST, Marc Renaudin).

Best regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/

 
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Mike Treseler
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      10-20-2003
Jamie wrote:
> I am trying to put together a state machine that is entirely
> asynchronous - NO CLK involved at all. But I just cant seem to get it
> to synthesize.


You would have to fight your synthesis tools
tools to get any asynch feedback.

If this is an intellectual exercise, use schematic entry.
If you want this to work, add a clock.


-- Mike Treseler

 
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Jamie
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      10-20-2003
Actually I figured it out. Just used StateCAD to create my state
machine with async reset and CLK'ed output. Verified operation then
removed the CLK dependencies of the processes.

viola! It works.


Renaud Pacalet <(E-Mail Removed)> wrote in message news:<bn0r4a$j2b$(E-Mail Removed)>...
> Jamie a écrit :
> > I am trying to put together a state machine that is entirely
> > asynchronous - NO CLK involved at all. But I just cant seem to get it
> > to synthesize.
> >

>
> Do you have a rough idea of the kind of hardware you expect? If not, then you're
> asking too much: a logic synthesizer just can't translate any VHDL description
> in hardware.
>
> > I have 2 port inputs, A and B, that I want to trigger the state
> > transitions and outputs. The structure im trying is something like the
> > following:
> >
> >
> > port(OBIT: out std_logic, A: in std_logic, B: in std_logic...)
> >
> > process(A, B..)
> > if (A='0') and (B='0') then
> > OBIT <= '0';
> > next_state <= S1;
> > end if;
> > .....
> > end process;

>
> What is your favourite asynchronous church? DI, QDI, SI, bundle data, dual rail
> encoding, two phases, four phases, other? Do you know what a Muller C-element
> is? Asynchronous design is something very specific, although some asynchronous
> priests pretend that synchronous design is just a sub-case of the much more
> general asynchronous design. You can't use the classical synchronous flow (VHDL
> + logic synthesizer) without any modification. Google will give you some
> pointers on using synchronous languages and CAD tools for asynchronous design
> (one key name: Daniel H. Linder) but you'll need, at least, a specific standard
> cells library... You can search for specific tools too (TAST, Marc Renaudin).
>
> Best regards,

 
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Renaud Pacalet
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Posts: n/a
 
      10-21-2003
Jamie a écrit :
> Actually I figured it out. Just used StateCAD to create my state
> machine with async reset and CLK'ed output. Verified operation then
> removed the CLK dependencies of the processes.
>
> viola! It works.
>


I'm affraid it doesn't at all. You're using VHDL to model something that has no
hardware equivalent. It simulates the way you want. OK. But you could also do it
in C++. By the way, after removing CLK from the sensivity list of your
synchronous processes, what signals remained?

Regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/

 
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Jamie
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      10-21-2003
Renaud Pacalet <(E-Mail Removed)> wrote in message news:<bn2tvn$bm3$(E-Mail Removed)>...
> Jamie a écrit :
> > Actually I figured it out. Just used StateCAD to create my state
> > machine with async reset and CLK'ed output. Verified operation then
> > removed the CLK dependencies of the processes.
> >
> > viola! It works.
> >

>
> I'm affraid it doesn't at all. You're using VHDL to model something that has no
> hardware equivalent. It simulates the way you want. OK. But you could also do it
> in C++. By the way, after removing CLK from the sensivity list of your
> synchronous processes, what signals remained?
>
> Regards,


I believe it does. All the signals remained. It simulates and synthesis completely.
 
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Renaud Pacalet
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      10-21-2003
Jamie a écrit :
> Renaud Pacalet <(E-Mail Removed)> wrote in message news:<bn2tvn$bm3$(E-Mail Removed)>...
>
>>Jamie a écrit :
>>
>>>Actually I figured it out. Just used StateCAD to create my state
>>>machine with async reset and CLK'ed output. Verified operation then
>>>removed the CLK dependencies of the processes.
>>>
>>>viola! It works.
>>>

>>
>>I'm affraid it doesn't at all. You're using VHDL to model something that has no
>>hardware equivalent. It simulates the way you want. OK. But you could also do it
>>in C++. By the way, after removing CLK from the sensivity list of your
>>synchronous processes, what signals remained?
>>
>>Regards,

>
>
> I believe it does. All the signals remained. It simulates and synthesis completely.


Well, a synchronous state machine is usually made of a synchronous state
register (with next state as data input, current state as data output, clock and
sync or async reset), a combinational circuit computing the next state from the
current state and the inputs and a combinational circuit computing the outputs
from the current state (and the inputs in case of a Meally machine). Usually
this leads to a single synchronous process modelling the state register or the
state register and the first combinational circuit plus one or more
combinational processes modelling the outputs computations. Usually the
sensivity list of the synchronous process contains only the clock and,
optionally, the asynchronous reset. So if you remove the clock you get an empty
list or the asynchronous reset, that is not much. Example with 3 processes:

type TSTATE is (S0, S1, S2);
signal STATE: TSTATE;
....
process(CLK, RSTN)
begin
if RSTN = '0' then
STATE <= S0;
elsif RISING_EDGE(CLK) then
case STATE is
when S0 => if IN0 = '1' then
STATE <= S1;
end if;
when S1 => STATE <= S2;
when S2 => if IN1 = '1' then
STATE <= S0;
end if;
end case;
end if;
end process;

OUT0 <= '1' when STATE = S0 else
'0';

OUT1<= '1' when STATE = S1 else
'0';

In this very simple example if you remove CLK from the sensivity list of the
synchronous process all you get is:

process(RSTN)
begin
if RSTN = '0' then
STATE <= S0;
elsif RISING_EDGE(CLK) then
case STATE is
when S0 => if IN0 = '1' then
STATE <= S1;
end if;
when S1 => STATE <= S2;
when S2 => if IN1 = '1' then
STATE <= S0;
end if;
end case;
end if;
end process;

I beleive most synthesizers will reject this with at least a bunch of warnings.
But if one does not then I can't imagine what it could synthesize. In case
StateCAD that I don't know puts every LHS signals in the sensivity list (some
tools do this, never understood why), after CLK removal you get:

process(RSTN, STATE, IN0, IN1)
begin
if RSTN = '0' then
STATE <= S0;
elsif RISING_EDGE(CLK) then
case STATE is
when S0 => if IN0 = '1' then
STATE <= S1;
end if;
when S1 => STATE <= S2;
when S2 => if IN1 = '1' then
STATE <= S0;
end if;
end case;
end if;
end process;

And I still can't imagine what could be synthesized from this. For my personal
culture could you give us your code before and after clock removal?

Best regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/

 
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fe
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Posts: n/a
 
      10-21-2003
>
> I beleive most synthesizers will reject this with at least a bunch of

warnings.
> But if one does not then I can't imagine what it could synthesize. In case
> StateCAD that I don't know puts every LHS signals in the sensivity list

(some
> tools do this, never understood why), after CLK removal you get:
>
> process(RSTN, STATE, IN0, IN1)
> begin
> if RSTN = '0' then
> STATE <= S0;
> elsif RISING_EDGE(CLK) then
> case STATE is
> when S0 => if IN0 = '1' then
> STATE <= S1;
> end if;
> when S1 => STATE <= S2;
> when S2 => if IN1 = '1' then
> STATE <= S0;
> end if;
> end case;
> end if;
> end process;
>
> And I still can't imagine what could be synthesized from this. For my

personal
> culture could you give us your code before and after clock removal?
>


Renaud,
Synthesizers don't need sensitivity list. The warning is only to tell you
that you will obtain different simulation result before and after synthesis.

process(rst_an)
begin
if rst_an = '0' then
....
elsif rising_edge(clk) then
...
end if;
end process;

is equivalent for the synthesizer to

process(rst_an, clk)
begin
if rst_an = '0' then
....
elsif rising_edge(clk) then
...
end if;
end process;

but not for the simulator. The warning is for that.

Jamie,
I don't know what you did but you can't simulate something and after that
modify it to synthesis. Circuit must have the same behaviour before and
after synthesis otherwise functional simulation is useless.

regards
fe
Sr ASIC Designer


 
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Renaud Pacalet
Guest
Posts: n/a
 
      10-22-2003
fe a écrit :

> Renaud,
> Synthesizers don't need sensitivity list. The warning is only to tell you
> that you will obtain different simulation result before and after synthesis.


I don't agree with that:

process(A, B)
begin
if A then
S <= B;
end if;
end process;

simulates and synthesizes as a latch while:

process(A)
begin
if A then
S <= B;
end if;
end process;

simulates and synthesizes as a DFF. This is an example where the sensivity list
is needed. I don't know if we could find another example... Any idea?

Regards,
--
Renaud Pacalet, GET/ENST/COMELEC/LabSoC
Institut Eurecom BP 193, 2229 route des Cretes
F-06904 Sophia-Antipolis Cedex
Tel : +33 (0) 4 9300 2770
Fax : +33 (0) 4 9300 2627
Fight Spam! Join EuroCAUCE: http://www.euro.cauce.org/

 
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Jamie
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Posts: n/a
 
      10-22-2003
Renaud Pacalet <(E-Mail Removed)> wrote in message news:<bn3k81$ir1$(E-Mail Removed)>...
> Jamie a écrit :
> > Renaud Pacalet <(E-Mail Removed)> wrote in message news:<bn2tvn$bm3$(E-Mail Removed)>...
> >
> >>Jamie a écrit :
> >>
> >>>Actually I figured it out. Just used StateCAD to create my state
> >>>machine with async reset and CLK'ed output. Verified operation then
> >>>removed the CLK dependencies of the processes.
> >>>
> >>>viola! It works.
> >>>
> >>
> >>I'm affraid it doesn't at all. You're using VHDL to model something that has no
> >>hardware equivalent. It simulates the way you want. OK. But you could also do it
> >>in C++. By the way, after removing CLK from the sensivity list of your
> >>synchronous processes, what signals remained?
> >>
> >>Regards,

> >
> >
> > I believe it does. All the signals remained. It simulates and synthesis completely.

>
> Well, a synchronous state machine is usually made of a synchronous state
> register (with next state as data input, current state as data output, clock and
> sync or async reset), a combinational circuit computing the next state from the
> current state and the inputs and a combinational circuit computing the outputs
> from the current state (and the inputs in case of a Meally machine). Usually
> this leads to a single synchronous process modelling the state register or the
> state register and the first combinational circuit plus one or more
> combinational processes modelling the outputs computations. Usually the
> sensivity list of the synchronous process contains only the clock and,
> optionally, the asynchronous reset. So if you remove the clock you get an empty
> list or the asynchronous reset, that is not much. Example with 3 processes:
>
> type TSTATE is (S0, S1, S2);
> signal STATE: TSTATE;
> ...
> process(CLK, RSTN)
> begin
> if RSTN = '0' then
> STATE <= S0;
> elsif RISING_EDGE(CLK) then
> case STATE is
> when S0 => if IN0 = '1' then
> STATE <= S1;
> end if;
> when S1 => STATE <= S2;
> when S2 => if IN1 = '1' then
> STATE <= S0;
> end if;
> end case;
> end if;
> end process;
>
> OUT0 <= '1' when STATE = S0 else
> '0';
>
> OUT1<= '1' when STATE = S1 else
> '0';
>
> In this very simple example if you remove CLK from the sensivity list of the
> synchronous process all you get is:
>
> process(RSTN)
> begin
> if RSTN = '0' then
> STATE <= S0;
> elsif RISING_EDGE(CLK) then
> case STATE is
> when S0 => if IN0 = '1' then
> STATE <= S1;
> end if;
> when S1 => STATE <= S2;
> when S2 => if IN1 = '1' then
> STATE <= S0;
> end if;
> end case;
> end if;
> end process;
>
> I beleive most synthesizers will reject this with at least a bunch of warnings.
> But if one does not then I can't imagine what it could synthesize. In case
> StateCAD that I don't know puts every LHS signals in the sensivity list (some
> tools do this, never understood why), after CLK removal you get:
>
> process(RSTN, STATE, IN0, IN1)
> begin
> if RSTN = '0' then
> STATE <= S0;
> elsif RISING_EDGE(CLK) then


> case STATE is
> when S0 => if IN0 = '1' then
> STATE <= S1;
> end if;
> when S1 => STATE <= S2;
> when S2 => if IN1 = '1' then
> STATE <= S0;
> end if;
> end case;
> end if;
> end process;
>
> And I still can't imagine what could be synthesized from this. For my personal
> culture could you give us your code before and after clock removal?
>
> Best regards,


My code follows. The commented out lines of code are what I removed to
be free of the clock.

-- VHDL code created by Xilinx's StateCAD 6.1i
-- Mon Oct 20 13:05:15 2003

-- This VHDL code (for use with Xilinx XST) was generated using:
-- enumerated state assignment with structured code format.
-- Minimization is enabled, implied else is disabled,
-- and outputs are speed optimized.

LIBRARY ieee;
USE ieee.std_logic_1164.all;


-- Finite State Machine to decode direction
-- of the HEDR-8000 OPTICAL SM ENCODER
-- ...00<->01<->11<->10...
ENTITY KDECODE IS
port (A,B: in std_logic;
--PORT (CLK,A,B,RESET: IN std_logic;
DBIT,UBIT : OUT std_logic);
attribute NOREDUCE: string;
END;

ARCHITECTURE BEHAVIOR OF KDECODE IS
TYPE type_sreg IS (S0,S1,S2,S3,S4,S5,S6,S7);
SIGNAL sreg, next_sreg : type_sreg;
SIGNAL next_DBIT,next_UBIT : std_logic;
attribute NOREDUCE of next_sreg: signal is "true";
BEGIN
process(next_sreg, next_DBIT, next_UBIT)
--PROCESS (CLK, RESET, next_sreg, next_DBIT, next_UBIT)
BEGIN
sreg <= next_sreg;
DBIT <= next_DBIT;
UBIT <= next_UBIT;
--IF ( RESET='1' ) THEN
-- sreg <= S0;
-- DBIT <= '0';
-- UBIT <= '0';
--ELSIF CLK='1' AND CLK'event THEN
-- sreg <= next_sreg;
-- DBIT <= next_DBIT;
-- UBIT <= next_UBIT;
--END IF;
END PROCESS;


PROCESS (sreg,A,B)
BEGIN
next_DBIT <= '0'; next_UBIT <= '0';

next_sreg<=S0;

CASE sreg IS
WHEN S0 =>
IF ( A='1' AND B='0' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
WHEN S1 =>
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( B='1' AND A='0' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
WHEN S2 =>
IF ( A='0' AND B='1' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
WHEN S3 =>
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( B='0' AND A='1' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
WHEN S4 =>
IF ( A='1' AND B='0' ) THEN
next_sreg<=S3;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
WHEN S5 =>
IF ( A='0' AND B='0' ) THEN
next_sreg<=S0;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( B='1' AND A='0' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
WHEN S6 =>
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( A='0' AND B='1' ) THEN
next_sreg<=S1;
next_DBIT<='0';
next_UBIT<='1';
END IF;
IF ( A='1' AND B='0' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S6;
next_DBIT<='1';
next_UBIT<='1';
END IF;
WHEN S7 =>
IF ( A='0' AND B='1' ) THEN
next_sreg<=S5;
next_UBIT<='0';
next_DBIT<='1';
END IF;
IF ( A='1' AND B='1' ) THEN
next_sreg<=S2;
next_DBIT<='0';
next_UBIT<='0';
END IF;
IF ( A='0' AND B='0' ) THEN
next_sreg<=S4;
next_DBIT<='1';
next_UBIT<='1';
END IF;
IF ( B='0' AND A='1' ) THEN
next_sreg<=S7;
next_UBIT<='0';
next_DBIT<='1';
END IF;
WHEN OTHERS =>
END CASE;
END PROCESS;
END BEHAVIOR;
 
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