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Hi all

Modelsim does not accept such a line :

CONSTANT version_number : std_logic_vector (7 downto 0) := X"0F";

Is this legal VHDL? Leonardo does accept it.
Modelsim says "Type error in bit string literal. Type std_logic_vector is not
an array of bit."

The only way I know so far to prevent this error is to write:

CONSTANT version_number : std_logic_vector (7 downto 0) :="00001111";

Which is possible here for only an 8-bit constant, but it gets truly
unreadable for a 32- bit constant.
How should I write this ?

Thanks
Roman

<> wrote in message
news:bmj2dj$fo4$...

> Modelsim does not accept such a line :
>
> CONSTANT version_number : std_logic_vector (7 downto 0) := X"0F";

Yes, it does. Switch on the VHDL-93 option in the compiler.
The X"..." notation was available only for BIT_VECTOR in VHDL-87,
but the syntax was cunningly hacked in -93 to make it work for
any vector whose elements include '0' and '1' in their value set.

One easy fix is to locate your system-wide modelsim.ini file
(somewhere in the ModelSim installation) and patch it - just look
at the file, it's easy to see what to do. When you've finished,
be very careful to mark the file read-only. Any new ModelSim
projects created in the future will use VHDL-93 as the default.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

An interesting follow-up, provoked by an email I received
directly (shame on you, Sir, but I'm respecting your
privacy by not exposing your email address here...)

> CONSTANT version_number : std_logic_vector (7 downto 0) := X"0F";
> I have not succeeded to use this coding style with vectors
> that are not a multiple of 4.
> Lets say you have a 6-bit vector and want to set it to 3F.
> Any suggestions?

No, this works only for multiples of 4 bits. The reason is
that VHDL-93 handles the idiom X"0F" by literally substituting
the string "00001111" - in other words, each hex digit always
creates four one-bit literals.

Put eight bits into a constant and take a slice of it, or
better, repackage the numeric_std RESIZE function to do
the job for you:

function resize_slv( s: std_logic_vector; n: positive )
return std_logic_vector is
begin
return std_logic_vector(resize(unsigned(s), n));
end;

....

constant version6: std_logic_vector(5 downto 0)
:= resize_slv(X"3F", 6);
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley <> wrote:
> <> wrote in message
> news:bmj2dj$fo4$...

>> Modelsim does not accept such a line :
>>
>> CONSTANT version_number : std_logic_vector (7 downto 0) := X"0F";

> Yes, it does. Switch on the VHDL-93 option in the compiler.
> The X"..." notation was available only for BIT_VECTOR in VHDL-87,
> but the syntax was cunningly hacked in -93 to make it work for
> any vector whose elements include '0' and '1' in their value set.

Thank you, that's it.

Roman

I've done something essentially the same in ModelSim (as included with
WebPack). I don't know why this wouldn't work for you, whether the
bit string length is 2 or 2000. I have one example in which I specify
the string length to be over 800 bits long and list it as a series of
ascii-hex digits:

constant madd : bit_vector(0 to mlength) := x"00a643156b23";

having assigned a value of 47 to length. There's also no reason why
this couldn't be ordered the other way, i.e. (mlength downto 0) in
order to accomplish what you stated. You can, of course, define it as
STD_LOGIC_VECTOR as well. I had to do both of the above in order to
specify the data as a complete packet, yet reverse the order of the
bits in bytewise fashion.

Being new to this VHDL stuff, I stubbed my toes on the various details
of data type assignment and conversion, but, once past that it seems
that ModelSim is quite standard in its treatment of this type of data.
I'd suspect that if you specify it as std_logic_vector(5 downto 0) or
(31 downto 0) and assign it a value of x"3f" you'll get what you want.
Now, it shouldn't surprise me if the 32-bit version requires the
leading zeroes in the hex.

Dick


wrote in message news:<bmj2dj$fo4$>...
> Hi all
>
> Modelsim does not accept such a line :
>
> CONSTANT version_number : std_logic_vector (7 downto 0) := X"0F";
>
> Is this legal VHDL? Leonardo does accept it.
> Modelsim says "Type error in bit string literal. Type std_logic_vector is not
> an array of bit."
>
> The only way I know so far to prevent this error is to write:
>
> CONSTANT version_number : std_logic_vector (7 downto 0) :="00001111";
>
> Which is possible here for only an 8-bit constant, but it gets truly
> unreadable for a 32- bit constant.
> How should I write this ?
>
> Thanks
> Roman