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Verilog/VHDL Simulation

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Can anyone tell me if the netlist generated by a simulator is language
specific or not...
like for eg. I generate code for the "same design" in both Verilog and
in VHDL and then simulate them using a single simulator, will the
netlist thats generated be the same..?
One may say Yes, coz ultimately what the simulator is doing is
generating "assembly language instructions" based on the design code,
so they shd be independent of the HDL....

But then I have seen studies where the code for similar Verilog and
VHDL designs had different number of code lines, and differnt no. of
"partitions(always block/process block)...and this might result in a
slightly diffenrt netlist being generated....

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Mike Treseler
Posts: n/a
Elf wrote:

> Can anyone tell me if the netlist generated by a simulator is language
> specific or not...

Synthesis generates a netlist.
Simulation generates a binary version of the source code
optimized for speed.

I would be surprised if either were identical for
vhdl and verilog versions of the same design.
The best way to answer this question is to
try it for a simple example.

-- Mike Treseler

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