Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Modelsim 5.7c behaviour

Reply
Thread Tools

Modelsim 5.7c behaviour

 
 
Ingmar Seifert
Guest
Posts: n/a
 
      10-08-2003
Hallo,

I use Modelsim 5.7c since yesterday. Before this I uses 5.6e.
I now get a warning when compiling a vhdl-file, in the following form:

WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
Warning: Signal "state" appears in process "steuerung"'s senstivity
list, but it is not used in the clock expression or reset expression.

I have set all signals, thta are read in a process in it's sensitivity
list. Former versions of modelsim showed an error, when the signal names
were missing. This version schows an error, when the signals are there.

What's wrong with my code or modelsim?


My code:
steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy, state,CLK,RESET)
BEGIN
IF RESET = '1' THEN
state <= IDLE;
div_xs_en <= '0';
xs_s <= (others=>'0');
ELSIF CLK'EVENT AND CLK='1' THEN
CASE state IS
-- IDLE = Startzustand nach RESET
WHEN IDLE =>
IF HU_UNIT_EN = '1' THEN
state <= XS;
END IF;
div_xs_en <= '0';

Thanks for your help in advance.
Regards,
Ingmar Seifert

 
Reply With Quote
 
 
 
 
Jim Wu
Guest
Posts: n/a
 
      10-08-2003

> WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
> Warning: Signal "state" appears in process "steuerung"'s senstivity
> list, but it is not used in the clock expression or reset expression.
>


> steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy,

state,CLK,RESET)

In a clocked process, only CLK and RESET need to be in the sensitivity list.

Jim Wu
http://www.velocityreviews.com/forums/(E-Mail Removed) (remove capital letters)
http://www.geocities.com/jimwu88/chips


 
Reply With Quote
 
 
 
 
Allan Herriman
Guest
Posts: n/a
 
      10-08-2003
On Wed, 08 Oct 2003 10:50:04 +0200, Ingmar Seifert
<(E-Mail Removed)-chemnitz.de> wrote:

>Hallo,
>
>I use Modelsim 5.7c since yesterday. Before this I uses 5.6e.
>I now get a warning when compiling a vhdl-file, in the following form:
>
>WARNING[10]: E:/Hu-Moment-Berechnung/src/hu_unit.vhd(162): Synthesis
>Warning: Signal "state" appears in process "steuerung"'s senstivity
>list, but it is not used in the clock expression or reset expression.
>
>I have set all signals, thta are read in a process in it's sensitivity
>list. Former versions of modelsim showed an error, when the signal names
>were missing. This version schows an error, when the signals are there.
>
>What's wrong with my code or modelsim?



The prevision version of Modelsim (5.6e) was wrong. The new version
(5.7c) is correct.
Previously, Modelsim would check that every signal used in the process
was in the sensitivity list. This is fine for combinatorial but wrong
for clocked processes.

Now, it can identify clocked processes (or clocked processes with
async resets), and checks that only the clocks and resets are in the
sensitivity list.

>My code:
>steuerung: PROCESS(HU_UNIT_EN, div_xs_quotient, div_xs_rdy, state,CLK,RESET)


should be:

>steuerung: PROCESS(CLK,RESET)


Regards,
Allan.
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
debugger behaviour different to execution behaviour Andy Chambers Java 1 05-14-2007 09:51 AM
xilinx logiblox and modelsim SE 5.6 Tim Terry VHDL 1 07-21-2003 03:25 PM
VHDL Simulation in ModelSim Manfred Balik VHDL 0 07-15-2003 02:12 PM
ModelSim Error Msg Yogi V. VHDL 3 07-03-2003 10:48 AM
Re: ModelSim 5.7 and xilinx libraries David Bishop VHDL 1 06-28-2003 04:53 PM



Advertisments