ModelSim & tcl testbench

I'm reasonably OK at writing VHDL code & testbenches, but I now need to
write a testbench in tcl rather than VHDL
so I can control the flow better. (I have a counter that wraps at 5
seconds, so i want to use FORCE to make it jump from a low to a high value,
by using the WHEN command in tcl.
(There's also a large counter that wraps every 550 years! Dont ask, it's
what the softies require, but even they can't explain).

However, I don't really know where to start although I have done some simple
tcl programming & scripting.

1. Do I just read in the VHDL design entity into ModelSim
2. Anyone have a sample/simple bit of code.
3. Point me a t the right website "tcl & modelsim for idiots" etc.

Regards, Niv.

--
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Niv

"Niv" <niv**mines_a_pint_you_spamheads**@ntlworld.com> wrote in
message news:V8Dgb.41$...

> I'm reasonably OK at writing VHDL code & testbenches, but I now
> need to write a testbench in tcl rather than VHDL so I can
> control the flow better.

VHDL can do control stuff pretty well, too... are you *sure* you need
a Tcl testbench?

> Dont ask, it's what the softies require, but even they can't explain

hmmm... I sympathise.

> 1. Do I just read in the VHDL design entity into ModelSim

You *can* do that, but you are likely to end up with a very inefficient
(slow) simulation because you need interaction between Tcl and the
simulator for each and every input signal transition. It's likely
to be far better to write the detailed time-dependent signal-wiggling
stuff in a VHDL test harness, and provide a few signals to control its
functionality. You can then manipulate those "control knobs" from
your Tcl jacket using [force] commands.

> 2. Anyone have a sample/simple bit of code.

Sure. Fancy coming on one of our Tcl courses?

You need to learn just three new ModelSim commands: [force], [when]
and [examine]. Read the docs on them, in detail. Note that you can
[force] signal changes planned for the future, and [examine] signal
values in the past; that means you don't need to stop and start the
sim very frequently, but instead you can run it in "batch mode",
setting-up numerous planned signal changes and then examining all
their effects when you eventually stop the sim.

> 3. Point me at the right website "tcl & modelsim for idiots" etc.

Not too many idiots visit our website, but you may still find a few
hints and code snippets at
www.doulos.com/knowhow/tcltk

We also have some nifty tricks for interaction between a running VHDL
sim and a Tcl program using pipes, but that is MUCH too interesting
to give away on the NG...

When you get really good at this stuff you will find yourself
controlling ModelSim from Tcl via a sockets interface. Ask your
friendly local Mentor rep about this, because the standard docs
don't say too much about it.

Enjoy.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

Niv wrote:
> I'm reasonably OK at writing VHDL code & testbenches, but I now need to
> write a testbench in tcl rather than VHDL

> (There's also a large counter that wraps every 550 years!

Consider passing the counter reset value to the entity
as a generic constant.

Make the default is all zero, so synthesis is not affected.

The VHLD testbench can then drive multiple instances
with different generic reset values,
say zero and 549.99999 years.

-- Mike Treseler

Mike Treseler