Functions

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I am trying to create a function in vhdl like this:


function gen_s (si, di :std_logic_vector)
return std_logic_vector is
begin
if (si(z_width) = '1') -- line 71
return (si(z_width-1 downto 0) & '0' ) + di; -- line 72
else
return si(z_width-1 downto 0) & '0' - di;
end if;
end gen_s;


It is inside of an architecture and I keep getting errors when
compiling in modelsim like this:

# ** Error: C:/dividers/div_uu.vhd(71): near "return": expecting:
GENERATE THEN
# ** Error: C:/dividers/div_uu.vhd(72): near "else": expecting: END_

What is wrong with this code that causes the errors above?

Salman Sheikh

Salman Sheikh wrote:

> I am trying to create a function in vhdl like this:
>
>
> function gen_s (si, di :std_logic_vector)
> return std_logic_vector is
> begin
> if (si(z_width) = '1') -- line 71
> return (si(z_width-1 downto 0) & '0' ) + di; -- line 72
> else
> return si(z_width-1 downto 0) & '0' - di;
> end if;
> end gen_s;
>
>
> It is inside of an architecture and I keep getting errors when
> compiling in modelsim like this:
>
> # ** Error: C:/dividers/div_uu.vhd(71): near "return": expecting:
> GENERATE THEN
> # ** Error: C:/dividers/div_uu.vhd(72): near "else": expecting: END_
>
> What is wrong with this code that causes the errors above?

It's actually a syntax error -- missing THEN before ELSE.
Not a very good error message.

The code below compiled ok for me

-- Mike Treseler

----------------------------------------------
constant z_width : natural := 8;
function gen_s (si, di : unsigned)
return unsigned is
begin
if (si(z_width) = '1') -- line 71
then
return (si(z_width-1 downto 0) & '0' ) + di; -- line 72
else
return si(z_width-1 downto 0) & '0' - di;
end if;
end gen_s;

Mike Treseler