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Help!
Doing a design in Virtex2 (XC2V250 so uite small).
The VHDL synthesises OK to an .edf file, plus another .edf for an IP core.

When I run PAR it fails the first hyurdle saying it can't find some blocks,
but why are they missing?

Message is "ngdbuild error 604"

Is it that 4.2 is old and can't fully handle Virtex2?

TIA, Niv.

Niv wrote:
> Help!
> Doing a design in Virtex2 (XC2V250 so uite small).
> The VHDL synthesises OK to an .edf file, plus another .edf for an IP core.
>
> When I run PAR it fails the first hyurdle saying it can't find some blocks,
> but why are they missing?

Your vhdl source should include an unbound component
and instance matching the ip name so that the
..edf files can be wired up correctly.

-- Mike Treseler

Yes, I realise all that, BUT, the some of the 5 error reports are pointing
to a section of the design that is all VHDL,
and nothing to do with the IP block. The other error messages refer to the
IP block, but I have put the IP .edf in the same
directory as the synthesised .edf for the whole chip.

So, I'm still confused.

PS. I've successfully done all this before with Virtex, on a different
design, with Xilinx "coregen" parts effectively as IP.
all this went just fine, but now with Virtex 2 I'm very stuck.

Niv.

"Mike Treseler" <> wrote in message
news:...
> Niv wrote:
> > Help!
> > Doing a design in Virtex2 (XC2V250 so uite small).
> > The VHDL synthesises OK to an .edf file, plus another .edf for an IP
core.
> >
> > When I run PAR it fails the first hyurdle saying it can't find some
blocks,
> > but why are they missing?
>
> Your vhdl source should include an unbound component
> and instance matching the ip name so that the
> .edf files can be wired up correctly.
>
> -- Mike Treseler
>