FF with CE doesn't synthesize correctly by XST?

Hi all,

I want the code below to synthesize as a FF with a sync reset and CE,
however XST does something quite different (target technology is Virtex II).
It routes my clk_ena signal to the REV pin and ties D and CE to VCC. The
sync_reset is recognized OK and gets routed correctly to the SR pin. I
realize that if I had a "regular" input signal instead of '1' under the
clock enable statement it would have worked fine, but what should I do if I
need to tie it to VCC?

process(clk)
begin
if rising_edge (clk) then
if sync_reset='1' then
outf <= '0';
elsif clk_ena='1' then
outf <= '1';
end if;
end if;
end process;

Thanks,
/Mikhail

MM

MM wrote:
> Hi all,
>
> I want the code below to synthesize as a FF with a sync reset and CE,
> however XST does something quite different (target technology is Virtex II).
> It routes my clk_ena signal to the REV pin and ties D and CE to VCC.

XST is just doing its job, making a valid netlist per your description.
A synth will often do unexpected things, but it will work just fine.

> The
> sync_reset is recognized OK and gets routed correctly to the SR pin. I
> realize that if I had a "regular" input signal instead of '1' under the
> clock enable statement it would have worked fine,

Both are "fine".
You write the description, the synth makes the netlist.

-- Mike Treseler


-- makes an fdre module on Virtex:
library ieee;
use ieee.std_logic_1164.all;

entity sreset_ce is
port (
clk : in std_ulogic;
clk_ena : in std_ulogic;
sync_reset : in std_ulogic;
inf : in std_ulogic;
outf : out std_ulogic);

end entity sreset_ce;

architecture synth of sreset_ce is
begin
process(clk) is
begin
if rising_edge (clk) then
if sync_reset = '1' then
outf <= '0';
elsif clk_ena = '1' then
outf <= inf;
end if;
end if;
end process;
end architecture synth;

Mike Treseler

Mikhail,
Your last statement suggests a solution.
Have you tried creating signal and assigning that to one outside of the process?

I this may (or may not) work.

If you absolutely want some particular interconnect configuration of a Xilinx
Basic Element you can always instantiate any component in the the unisim library

(unisim_VCOMP.vhd) FDRE in this case

I'll also just mention XST implementation is logically correct even if it wasn't
what
you wanted.

Chris



MM wrote:

> Hi all,
>
> I want the code below to synthesize as a FF with a sync reset and CE,
> however XST does something quite different (target technology is Virtex II).
> It routes my clk_ena signal to the REV pin and ties D and CE to VCC. The
> sync_reset is recognized OK and gets routed correctly to the SR pin. I
> realize that if I had a "regular" input signal instead of '1' under the
> clock enable statement it would have worked fine, but what should I do if I
> need to tie it to VCC?
>
> process(clk)
> begin
> if rising_edge (clk) then
> if sync_reset='1' then
> outf <= '0';
> elsif clk_ena='1' then
> outf <= '1';
> end if;
> end if;
> end process;
>
> Thanks,
> /Mikhail

Chris Ebeling

"Mike Treseler" <> wrote in message
news:...
> MM wrote:
> > Hi all,
> >
> > I want the code below to synthesize as a FF with a sync reset and CE,
> > however XST does something quite different (target technology is Virtex
II).
> > It routes my clk_ena signal to the REV pin and ties D and CE to VCC.
>
> XST is just doing its job, making a valid netlist per your description.
> A synth will often do unexpected things, but it will work just fine.

I don't think the netlist is valid. With D and CE both tied to VCC the flop
reverts to '1' on every clock regardless of my clk_ena signal. This is a
part of a bigger design that used to work on Spartan II. I only found the
problem when I moved it to Virtex II.... Any other ideas?

Thanks,
/Mikhail

MM

MM wrote:

> I don't think the netlist is valid. With D and CE both tied to VCC the flop
> reverts to '1' on every clock regardless of my clk_ena signal.

Your description says outf is low for reset, high otherwise.
The only way to get a low with that description
is to reset and immediately disble the clock.

-- Mike Treseler

Mike Treseler

OK, so how should I describe a D flip-flop with a synchronous reset and a
clock enable with the D input tied to VCC?

/Mikhail


"Mike Treseler" <> wrote in message
news:...
> MM wrote:
>
> > I don't think the netlist is valid. With D and CE both tied to VCC the
flop
> > reverts to '1' on every clock regardless of my clk_ena signal.
>
> Your description says outf is low for reset, high otherwise.
> The only way to get a low with that description
> is to reset and immediately disble the clock.
>
> -- Mike Treseler
>

MM

"Chris Ebeling" <> wrote in message
news:...
> Mikhail,
> Your last statement suggests a solution.
> Have you tried creating signal and assigning that to one outside of the
process?
>
> I this may (or may not) work.

Tried, it doesn't work.

> If you absolutely want some particular interconnect configuration of a
Xilinx
> Basic Element you can always instantiate any component in the the unisim
library
>
> (unisim_VCOMP.vhd) FDRE in this case

I would like to avoid this.

> I'll also just mention XST implementation is logically correct even if it
wasn't
> what
> you wanted.

So, is there a way to describe what I want in VHDL so that XST will
understand it?

/Mikhail

MM

You could try to break your process into two seperate ones. Sometimes
"rewording" your code has an effect on the synthesizer:

process(clk,inf)
begin
if rising_edge(clk) then
outf <= inf;
end if;
end process;

process(sync_reset,clk_ena,outf)
begin
if sync_reset = '1' then
inf <= '0';
elsif clk_ena = '1' then
inf <= '1';
else
inf <= outf;
end if;
end process;

If you get desperate, you can manually instantiate a FF. It won't be as
portable, of course.

From what code you have shown us, I can't see why the XST is doing what it's
doing, unless the logic generating sync_reset and clk_ena is somehow causing
you problems. You could run a quick experiment and synthesize only that
piece of FF code, in your post, making sync_reset and clk_ena into ports, to
see what the synthesizer does.

Best of luck.


Regards,
Vinh

Vinh Pham

I've just tried synthesizing the same code for Spartan II. The result is
similar in terms of using REV pin, however in this case the D and CE are
(correctly in my opinion) tied to GND!

So, at the very least the synthesis results are not consistent and I still
think the netlist for Virtex II is not valid.

/Mikhail

MM

I agree with Mikhail. The real problem is CE being connected to VCC. If it
was connected to GND (doesn't matter what D is connected to), things would
be fine.

Vinh Pham