VHDL - Resume: Design Verification Consultant (Specman)

09-25-2003, 04:53 PM

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<td width=621 valign=top style='width:465.65pt;border:none;border-bottom:
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Christopher R. Starr
</td>
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<a
href="private.php?do=newpm&u=">veritec@austin .rr.com</a><o

></o

>

<o

> </o

>

SPECIAL
SKILLS

<o

> </o

>

<div align=center>

<table class=MsoNormalTable border=0 cellspacing=0 cellpadding=0
style='border-collapse:collapse;mso-padding-alt:0in 2.15pt 0in 2.15pt'>
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VLSI CAD Tools<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
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2.15pt'>
Cadence,
Verisity, Viewlogic,
VCS,
MTI, Verilog-XL, VHDL, Speedsim, Specman,
<st1

lace
w:st="on">Denali</st1

lace>, SKILL, Composer, ViewDraw,
Smartmodels, Hardware Models<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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Telecom<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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2.15pt'>
Sonet, STS-1, STS-3, STS-12, DS1,
DS3, VT 1.5<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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padding:0in 2.15pt 0in 2.15pt'>
Avionics<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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2.15pt'>
Fuel
Measurement/Management Systems, Full Authority Digital Engine Controls,
Electronic Flight Instrumentation Systems<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
Methodologies<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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2.15pt'>
DO-178A,
MIL-STD-2167A, OOD, OOP<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
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Languages<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
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windowtext .75pt;
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2.15pt'>
C++,
Pascal, PLM, FORTRAN, <st1

lace w:st="on">FORTH</st1

lace>, MAILSAIL,
MIL-STD-1750A (Fairchild 9450), 80x86, 68000 Assembler<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
Compiler Tools<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
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windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
LEX,
Perl, YACC, FLEX, BISON (specialist in application
specific compilers)<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
Operating Systems<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
windowtext 1.5pt;
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windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
UNIX,
Solaris, AIX, VAX/VMS, MS-DOS, HP/UX<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
Hardware<o

></o

>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
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windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
PC,
VAX, Sun, HP-700, RS6000<o

></o

>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:solid windowtext 1.5pt;
border-right:none;mso-border-top-alt:solid windowtext
..75pt;mso-border-left-alt:
solid windowtext .75pt;mso-border-bottom-alt:solid windowtext 1.5pt;
padding:0in 2.15pt 0in 2.15pt'>
Communications<o

></o

>
</td>
<td width=448 valign=top
style='width:336.0pt;border-top:1.0pt;border-left:
1.0pt;border-bottom:1.5pt;border-right:1.5pt;border-color:windowtext;
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PCI
2.2, PCI-X, GPIB, MIL-STD-1553, ISDN BRI, ARINC<o

></o

>
</td>
</tr>
</table>

</div>

<o

> </o

>

PROFESSIONAL
EXPERIENCE<o

></o

>

<o

> </o

>

MAY03-SEP03 Intel, ICG Division, <st1

lace
w:st="on"><st1:City
w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1

lace>. Responsible for the implementation of
several
functional coverage plans for the host interface of a LAN access chip. Functional coverage was implemented using
Verisitys' Specman language. The simulation platform was MTI using
Verilog
design components. Interfaces of
interest include PCI, PCI-X 1.0b, PCI-Express and TCP/IP. The hardware platform was an X86 based PC
running Redhat Linux.<o

></o

>

<o

> </o

>

JAN03-MAY03 Inrange Technologies, <st1

lace
w:st="on"><st1:City
w:st="on">Lumberton</st1:City>, <st1:State w:st="on">New
Jersey</st1:State></st1

lace>. Helped complete
verification of a fibre channel switch
platform. The test bench was written using Verisitys' Specman language. The simulation platform was MTI using a
mix
of Verilog and VHDL design components.
Duties included test bench enhancements and system-level verification
of
the design. The hardware platform was an X86 based PC running Redhat Linux.<o

></o

>

<o

> </o

>

FEB01-JUL02 Agere Systems, <st1

lace
w:st="on"><st1:City
w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1

lace>.  Responsible for
the
design and implementation of simulation test bench drivers to configure a
network processor chipset.  The test bench was implemented using
Specman
e-code and <st1

lace w:st="on">Denali</st1

lace> memory models. Some
highlights of the configuration code include: <o

></o

>

<o

> </o

>

<![if !supportLists]>·         
<![endif]>Register/memory access via PCI cycles or PCI DMA transfers or RTL
hierarchy.  Access via RTL hierarchy would allow configuration to be
completed in zero-time. Configuration
access mode could be switched with a run time flag (no test case
changes).<o

></o

>

<![if !supportLists]>·         
<![endif]>High-level register/memory access interfaces to simplify test case
writing.  The test case writers would interface with abstract
system-level
data structures instead of low-level bits and bytes. <o

></o

>

<![if !supportLists]>·         
<![endif]>Automated configuration of complex memory architectures (FCRAM,
QDRRAM). <o

></o

>


<o

></o

>

 Also
worked as a general resource for netlist bring-up
and
test case debugging.<o

></o

>

<o

> </o

>

AUG99-FEB01 Analog Devices/Intel Joint Development
Project, <st1

lace w:st="on"><st1:City w:st="on">Austin</st1:City>,
<st1:State
w:st="on">Texas</st1:State></st1

lace>.  Responsible for
the
design and implementation of a simulation test bench for a new DSP core
being
developed jointly by ADI and Intel.  The test bench was
implemented
in Verilog (XL/VCS/NCVLOG). Some highlights of the test bench
include:<o

></o

>

<o

> </o

>

<![if !supportLists]>·         
<![endif]>Ability to load program code into L2-memory and instruction-cache
memory.<o

></o

>

<![if !supportLists]>·         
<![endif]>Ability to load program data into L2-memory and data-cache
memory.<o

></o

>

<![if !supportLists]>·         
<![endif]>Integration of an architectural reference model for the DSP core
into
the test bench. <o

></o

>

<![if !supportLists]>·         
<![endif]>Automated checking of register value changes using data from the
reference model. <o

></o

>

<![if !supportLists]>·         
<![endif]>Implementation of the entire 4GB L2 memory space using a sparse
memory
model. <o

></o

>

<![if !supportLists]>·         
<![endif]>Automated checking of program counter changes due to interrupts and
exceptions. <o

></o

>

<![if !supportLists]>·         
<![endif]>Very fast instruction execution (approximately 350 instruction
per second using compiled simulation). <o

></o

>

<![if !supportLists]>·         
<![endif]>Scripting language to control core inputs and to test core outputs
(resets, clocks, interrupts, exceptions, configuration pins, etc.).
<o

></o

>


<o

></o

>

 Also
worked on a chip being developed solely by ADI using the DSP
core. 
This chip included the DSP core, a bridge from the core to several Amba
buses
(high and low speed), L2-memory, SDRAM controller, SRAM controller and
various
on-chip Amba bus peripherals (UART, SPORT, SPI, DMA engines, etc.).  My
work involved real-time troubleshooting of the test bench and netlist to enable test case writing to
continue.

<o

> </o

>

MAR99-AUG99
Compaq,
<st1

lace w:st="on"><st1:City w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1

lace>. Responsible for the
block-level verification of a PCI-X megacell.
The
megacell converted PCI-X transactions to and from a proprietary on-chip interface
bus. Developed test plans, coded a
random PCI-X transaction
generator
for stress testing the megacell (using Verilog-XL), implemented test cases,
and helped supervise a group of co-op students at Texas A&M
also working on the project.<o

></o

>

<o

> </o

>

Nov97-MAR99
AMD,
<st1

lace w:st="on"><st1:City w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1

lace>. Responsible for the system-level
verification
of a system-on-a-chip consisting of an x86 microprocessor core, PCI host
bridge, SDRAM controller, ROM controller and various PC/AT compatible
devices
(8237 DMA, UARTs, RTC, PIC, etc.). The system test bench environment was
constructed using Verisitys' e-language based verification tool
(Specman) integrated with Verilog-XL based bus function models
(PCI bus, x86 bus, SDRAM devices, ROM devices, etc.) 

<o

> </o

>

Nov96-Oct97
IBM,
Microelectronics Division, <st1

lace w:st="on"><st1:City w:st="on">Research
Triangle Park</st1:City>, <st1:State w:st="on">North
Carolina</st1:State></st1

lace>. Responsible for the system-level
verification
of a 1100K gate set-top-box ASIC. Developed bus functional models for
several
internal interconnect buses using C++. These models would interface to SpeedSims' cycle-based simulator through the standard
PLI
interface. Developed and implemented test suites to verify the connectivity
of
the microprocessor core, cross-bar switch, MPEG-2 video and audio decoders,
DRAM, SRAM, SDRAM and other off-chip interfaces.<o

></o

>

<o

> </o

>

Jun 95-Nov 96
Cisco Systems, <st1

lace w:st="on"><st1:City
w:st="on">Research Triangle
Park</st1:City>, <st1:State
w:st="on">North
Carolina</st1:State></st1

lace>. Responsible for the system-level verification of the Cisco 7200 series
router. Developed verification
tools and turnkey regression test suites for three high-density printed
circuit
cards. Verification was done
using the Cadence Verilog-XL simulator, Synopsys
SmartModels and hardware models. System-level regression test suite was
written primarily in Synopsys PCL code. A Verilog behavioral model was created to
simulate the bus activity generated by various port adapter cards which plug
into
the router chassis via a PCI bus interface.<o

></o

>

<o

> </o

>

 Also
developed a chip-level test bench for an ASIC that bridges token-ring frames
from a proprietary switching bus to a PCI bus. The test bench was developed using Specman (a next-generation
verification
tool from Verisity).
This tool was used to automatically generate token-ring frame
stimulus
and verify that the frame data was passed correctly through the chip based
on
the destination address, <st1

lace w:st="on">RIF</st1

lace>, SNAP and DSAP
fields.<o

></o

>

<o

> </o

>

Feb94-Jun95
Alcatel Network Systems, <st1

lace w:st="on"><st1:City
w:st="on">Raleigh</st1:City>,
<st1:State w:st="on">North
Carolina</st1:State></st1

lace>. Developed drivers and
monitors (Verilog-XL) to generate
and analyze STS-1, STS-3 and STS-12 stimulus patterns for an ASIC chipset
being
used in Alcatels' next generation SONET switches.
These drivers/monitors were integrated into a user-friendly test bench to
expedite system- level verification of the chipset.<o

></o

>

<o

> </o

>

Feb92-Feb94 IBM,
Network Systems, <st1

lace w:st="on"><st1:City w:st="on">Research Triangle
Park</st1:City>, <st1:State w:st="on">North
Carolina</st1:State></st1

lace>. Developed
behavioral models (Verilog-XL) to
simulate the system-level environment of a full motion video co-processor
for
an IBM-PC graphics adapter card. Responsible for
the
implementation of full chip simulation scenarios to test capabilities of the
co-processor which included scaling, cropping, dithering and YUV-RGB
conversion. Behavioral models
generated
for system level functions included VRAMs, NTSC
and
compressed video data sources, host computer data source, memory bus
arbitration module and assorted analysis modules to track data flow inside
and
outside of the chip.<o

></o

>

<o

> </o

>

Nov88-Feb92
Honeywell, Commercial Flight Systems, <st1

lace w:st="on"><st1:City
w:st="on">Phoenix</st1:City>,
<st1:State w:st="on">Arizona</st1:State></st1

lace>. Designed, coded and tested software to
perform branch and code coverage analysis on an electronic flight
instrumentation system for the MD-11 commercial aircraft. This package consisted of: a pre-processor
(VAX C) to determine the possible
branches taken by the flight software; a mid-processor (80386 Assembler) to record the actual branches taken; a
post-processor (VAX C) to compare
the possible with the actual branches and produce a coverage report
detailing
any unexecuted code or branches.
Also,
developed software to provide symbology for 80386 emulation on an HP9000 workstation. Also, developed software
to
facilitate functional testing of the flight
software.<o

></o

>

<o

> </o

>

 Developed
a unique testing tool which allowed component integration-level tests to be
generated automatically from individual component-level tests resulting in a
dramatic reduction in man-hours required to certify the flight
software. <o

></o

>

<o

> </o

>

 Developed
a code-scanning compiler to verify the integrity of manually entered
data-dictionary information with procedure/variable references from the
source
code.<o

></o

>

<o

> </o

>

Feb88-Aug88
<st1:City
w:st="on">Hamilton</st1:City>
Standard, <st1:City
w:st="on">Windsor</st1:City>
Locks, <st1:State w:st="on"><st1

lace
w:st="on">Connecticut</st1

lace></st1:State>. Designed, coded and tested software to
perform diagnostic testing on Full Authority Digital Engine Controls (FADEC) for large military jet
engines. Software was written in
Pascal
for an HP9000.<o

></o

>

<o

> </o

>

Oct87-Feb88 AT&T Information Systems,
<st1

lace
w:st="on"><st1:City w:st="on">Denver</st1:City> <st1:State
w:st="on">Colorado</st1:State></st1

lace>. Designed, coded and
tested
software to perform diagnostic testing on ISDN
BRI compatible terminals for the System 85 PBX.<o

></o

>

<o

> </o

>

Oct86-Oct87
Simmonds Precision, <st1

lace w:st="on"><st1:City w:st="on">Vergennes</st1:City>,
<st1:State
w:st="on">Vermont</st1:State></st1

lace>. Designed, coded and tested software to
perform diagnostic testing on a fuel measurement and management system for
military aircraft. This package
consisted of software running in the flight computer (MIL-STD-1750A or Fairchild 9450) to perform functional testing
of
the hardware and software running on an IBM-PC (Microsoft C & 8088 Assembler) to control test execution and
error logging. Challenges of this
assignment: a wide variety of communications interfaces (RS-232, IEEE 488, MIL-STD-1553); customized interrupt handlers
(UART, keyboard, timer); a wide variety of test equipment (HP6032A Power
Supply, LORAL SBA 100A, Control Systems Research MICRISTAR). Extensive documentation (MIL-STD-2167A) was produced to satisfy the standards and
procedures of military contracts.
Also, developed a Software Source Control System to help
maintain
customized releases of this package.<o

></o

>

<o

> </o

>

Feb86-May86
General Electric, Co., <st1

lace w:st="on"><st1:City
w:st="on">Somersworth</st1:City>,
<st1:State w:st="on">New Hampshire</st1:State></st1

lace>. Made bug fixes/enhancements to EPROM
burning
software (FORTRAN 77) used by GE
to
program their line of demand recording meters.
These enhancements included the ability to handle 256K EPROMs, validation testing features and changing file
allocation from static to dynamic.<o

></o

>

<o

> </o

>

Feb85-Feb86
Versatile Systems, Inc., <st1

lace w:st="on"><st1:City
w:st="on">Belmont</st1:City>,
<st1:State w:st="on">California</st1:State></st1

lace>. Designed, coded and tested software to
translate the database of one PC-based architectural drawing program to
another. Also,
developed a customized PILOT language
interpreter.<o

></o

>

<o

> </o

>

Mar82-Feb85
VLSI Technology, Inc., <st1

lace w:st="on"><st1:City w:st="on">San
Jose</st1:City>,
<st1:State w:st="on">California</st1:State></st1

lace>. Major contributor to the
cell
compiler project. This is
a
library of customized hardware components generated by a collection
of
software elements called cell compilers.
These cells, by allowing a logic designer to create flexible building
blocks (i.e., registers, counters, ALUs), can
significantly reduce the time required to develop an ASIC. Consultant for several custom chip
projects: Macintosh Computer for
Apple,
Atari home video game, Cable TV descrambler, Display Controller for a
portable
PC. These projects encompassed all
aspects of VLSI chip design from schematic entry/logic simulation to cell
layout/chip composition.<o

></o

>

<o

> </o

>

Jun81-Mar82
Hewlett Packard, Disc Memory Division, <st1

lace w:st="on"><st1:City
w:st="on">Boise</st1:City>,
<st1:State w:st="on">Idaho</st1:State></st1

lace>. Designed, coded and tested software to
automatically generate PLAs for VLSI chips. This package consisted of: a compiler to
convert a high-level language description of the finite state machine
behavior
to truth tables; a logic minimizer to reduce the
truth tables; a PLA generator to convert the truth tables to mask
geometry.<o

></o

>

<o

> </o

>

Sep73-Jun75
<st1

laceName
w:st="on">South</st1

laceName> <st1

laceName w:st="on">Burlington</st1

laceName> <st1

laceType
w:st="on">High School</st1

laceType>, <st1

lace w:st="on"><st1:City w:st="on">South
Burlington</st1:City>, <st1:State
w:st="on">Vermont</st1:State></st1

lace>. Designed, coded and tested software to
perform class scheduling, produce class lists and to maintain attendance
records
for the school.<o

></o

>

<o

> </o

>

EDUCATION

<o

> </o

>

June 1981
Master of Science in
Electrical Engineering program, <st1

laceName
w:st="on">Dartmouth</st1

laceName>
<st1

laceType w:st="on">College</st1

laceType>, Thayer School of
Engineering,
Hanover, <st1

lace w:st="on"><st1:State w:st="on">New
Hampshire</st1:State></st1

lace>.
One year credit toward degree.<o

></o

>

<o

> </o

>

June 1980
Bachelor of Science in
Computer Science with a minor in electrical engineering, Michigan State
University, East Lansing, Michigan.
Graduated cum laude.<o

></o

>

<o

> </o

>

PATENTS
<st1:country-region
w:st="on"><st1

lace w:st="on">United
States</st1

lace></st1:country-region> Patent
#6,052,745, System for asserting burst termination signal and
burst
complete signal one cycle prior to and during last cycle in fixed length
burst
transfers. <o

></o

>

PUBLICATIONS

<o

> </o

>

 [1]
Cell Compilers vs. Standard Cell
Design,
Custom Integrated Circuits Conference, <st1

lace w:st="on"><st1:City
w:st="on">Rochester</st1:City>,
<st1:State w:st="on">NY</st1:State></st1

lace>,
1984.<o

></o

>

<o

> </o

>

 [2]
Cell Layout Compilers Simplify Custom IC
Design, EDN, September 15,
1983.<o

></o

>

<o

> </o

>

 [3]
Automatic PLA Generation, Hewlett
Packard VLSI Conference, <st1

lace w:st="on"><st1:City w:st="on">Corvalis</st1:City>, <st1:State
w:st="on">Oregon</st1:State></st1

lace>,
1981.<o

></o

>

<o

> </o

>

</div>

</body>

</html>

Veritec

09-25-2003, 06:51 PM

You seriously anyone would read something in some vague MS XML format ?
I doubt it...

Igmar

Igmar Palsenberg

09-26-2003, 08:24 PM

Igmar Palsenberg <news-> wrote in message news:<3f732c73$0$58710$>...
> You seriously anyone would read something in some vague MS XML format ?
> I doubt it...

This part was funny:

<o:LastAuthor>Sam Gamgee</o:LastAuthor>

Yep, he's hired. Starts tomorrow.

Thank you, drive through.

-a

Andy Peters

09-25-2003, 06:51 PM	#2
Igmar Palsenberg Posts: n/a	Re: Resume: Design Verification Consultant (Specman) You seriously anyone would read something in some vague MS XML format ? I doubt it... Igmar Igmar Palsenberg

09-26-2003, 08:24 PM	#3
Andy Peters Posts: n/a	Re: Resume: Design Verification Consultant (Specman) Igmar Palsenberg <news-> wrote in message news:<3f732c73$0$58710$>... > You seriously anyone would read something in some vague MS XML format ? > I doubt it... This part was funny: <o:LastAuthor>Sam Gamgee</o:LastAuthor> Yep, he's hired. Starts tomorrow. Thank you, drive through. -a Andy Peters

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