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Resume: Design Verification Consultant (Specman)

 
 
Veritec
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      09-25-2003
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<p class=TableText align=center style='text-align:center'><b
style='mso-bidi-font-weight:normal'><span
style='font-size:14.0pt;mso-bidi-font-size:
10.0pt;font-family:"Times New Roman"'>Christopher R. Starr</span></b></p>
</td>
</tr>
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<p class=DefaultText align=center style='text-align:center'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><a
href="(E-Mail Removed)">veritec@austin .rr.com</a></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Times New
Roman"'><o></o></span></p>

<p class=DefaultText><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Arial MT"'><o>&nbsp;</o></span></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'>SPECIAL
SKILLS</span></p>

<p class=DefaultText><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Arial MT"'><o>&nbsp;</o></span></p>

<div align=center>

<table class=MsoNormalTable border=0 cellspacing=0 cellpadding=0
style='border-collapse:collapse;mso-padding-alt:0in 2.15pt 0in 2.15pt'>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
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windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>VLSI CAD Tools</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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windowtext 1.5pt;
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windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>Cadence,
<span class=SpellE>Verisity</span>, <span class=SpellE>Viewlogic</span>,
VCS,
MTI, Verilog-XL, VHDL, <span class=SpellE>Speedsim</span>, Specman,
<st1lace
w:st="on">Denali</st1lace>, SKILL, Composer, <span
class=SpellE>ViewDraw</span>,
<span class=SpellE>Smartmodels</span>, Hardware Models</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Telecom</span></b><span
style='font-size:
11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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windowtext 1.5pt;
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windowtext .75pt;
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2.15pt'>
<p class=TableText><span class=SpellE><b
style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>Sonet</span></b></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:
Arial;mso-bidi-font-family:"Times New Roman"'>, STS-1, STS-3, STS-12, DS1,
DS3, VT 1.5</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Arial MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Avionics</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
windowtext 1.5pt;
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windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>Fuel
Measurement/Management Systems, Full Authority Digital Engine Controls,
Electronic Flight Instrumentation Systems</span></b><span
style='font-size:
11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Methodologies</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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windowtext 1.5pt;
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windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>DO-178A,
MIL-STD-2167A, OOD, OOP</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;font-family:"Arial MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
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mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Languages</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
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windowtext 1.5pt;
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windowtext .75pt;
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2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>C++,
Pascal, PLM, FORTRAN, <st1lace w:st="on">FORTH</st1lace>, MAILSAIL,
MIL-STD-1750A (Fairchild 9450), 80x86, 68000 Assembler</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Compiler Tools</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
windowtext 1.5pt;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>LEX,
Perl, YACC, FLEX, BISON</span></b><span
style='font-size:10.0pt;font-family:
Arial;mso-bidi-font-family:"Times New Roman"'> (specialist in application
specific compilers)</span><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;font-family:"Arial MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Operating Systems</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
windowtext 1.5pt;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>UNIX,
Solaris, AIX, VAX/VMS, MS-DOS, HP/UX</span></b><span
style='font-size:11.0pt;
mso-bidi-font-size:10.0pt;font-family:"Arial MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:none;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Hardware</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top style='width:336.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:none;border-right:solid
windowtext 1.5pt;
mso-border-top-alt:solid windowtext .75pt;mso-border-left-alt:solid
windowtext .75pt;
mso-border-right-alt:solid windowtext 1.5pt;padding:0in 2.15pt 0in
2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>PC,
VAX, Sun, HP-700, RS6000</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;font-family:"Arial MT"'><o></o></span></p>
</td>
</tr>
<tr style='mso-yfti-irow:0;mso-yfti-firstrow:yes;mso-yfti-lastrow:yes'>
<td width=172 valign=top style='width:129.0pt;border-top:solid windowtext
1.0pt;
border-left:solid windowtext 1.0pt;border-bottom:solid windowtext 1.5pt;
border-right:none;mso-border-top-alt:solid windowtext
..75pt;mso-border-left-alt:
solid windowtext .75pt;mso-border-bottom-alt:solid windowtext 1.5pt;
padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText style='margin-left:6.85pt'><b
style='mso-bidi-font-weight:
normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
Technical;text-transform:uppercase'>Communications</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
<td width=448 valign=top
style='width:336.0pt;border-top:1.0pt;border-left:
1.0pt;border-bottom:1.5pt;border-right:1.5pt;border-color:windowtext;
border-style:solid;mso-border-top-alt:.75pt;mso-border-left-alt:.75pt;

mso-border-bottom-alt:1.5pt;mso-border-right-alt:1.5pt;mso-border-color-alt:
windowtext;mso-border-style-alt:solid;padding:0in 2.15pt 0in 2.15pt'>
<p class=TableText><b style='mso-bidi-font-weight:normal'><span
style='font-size:10.0pt;font-family:Arial;mso-bidi-font-family:"Times New
Roman"'>PCI
2.2, PCI-X, GPIB, MIL-STD-1553, ISDN BRI, ARINC</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o></o></span></p>
</td>
</tr>
</table>

</div>

<p class=DefaultText><b style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:"Arial
MT"'><o>&nbsp;</o></span></b></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'>PROFESSIONAL
EXPERIENCE<o></o></span></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'><o>&nbsp;</o></span></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>MAY03-SEP03<span style='mso-tab-count:1'> </span><b
style='mso-bidi-font-weight:normal'>Intel, ICG Division</b>, <st1lace
w:st="on"><st1:City
w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Responsible for the implementation of
several
functional coverage plans for the host interface of a LAN access chip.<span
style='mso-spacerun:yes'> </span>Functional coverage was implemented using
<span
class=SpellE>Verisitys</span>' Specman language.<span
style='mso-spacerun:yes'> </span>The simulation platform was MTI using
Verilog
design components.<span style='mso-spacerun:yes'> </span>Interfaces of
interest include PCI, PCI-X 1.0b, PCI-Express and TCP/IP.<span
style='mso-spacerun:yes'> </span>The hardware platform was an X86 based PC
running <span class=SpellE>Redhat</span> Linux.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>JAN03-MAY03<span style='mso-tab-count:1'> </span><span
class=SpellE><b style='mso-bidi-font-weight:normal'>Inrange</b></span><b
style='mso-bidi-font-weight:normal'> Technologies</b>, <st1lace
w:st="on"><st1:City
w:st="on">Lumberton</st1:City>, <st1:State w:st="on">New
Jersey</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span><span class=GramE>Helped complete
verification of a <span class=SpellE>fibre</span> channel switch
platform.</span><span
style='mso-spacerun:yes'> </span>The test bench was written using <span
class=SpellE>Verisitys</span>' Specman language.<span
style='mso-spacerun:yes'> </span>The simulation platform was MTI using a
mix
of Verilog and VHDL design components.<span style='mso-spacerun:yes'>
</span>Duties included test bench enhancements and system-level verification
of
the design. The hardware platform was an X86 based PC running <span
class=SpellE>Redhat</span> Linux.<o></o></span></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'><o>&nbsp;</o></span></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>FEB01-JUL02<span style='mso-tab-count:1'> </span><span
class=SpellE><b style='mso-bidi-font-weight:normal'>Agere</b></span><b
style='mso-bidi-font-weight:normal'> Systems</b>, <st1lace
w:st="on"><st1:City
w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>&nbsp; Responsible for
the
design and implementation of simulation test bench drivers to configure a
network processor chipset.&nbsp; The test bench was implemented using
Specman
e-code and <st1lace w:st="on">Denali</st1lace> memory models. Some
highlights of the configuration code include: <o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l2 level1 lfo2;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Register/memory access via PCI cycles or PCI DMA transfers or RTL
hierarchy.&nbsp; Access via RTL hierarchy would allow configuration to be
completed in zero-time.<span style='mso-spacerun:yes'> </span>Configuration
access mode could be switched with a run time flag (no test case
changes).<o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l2 level1 lfo2;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>High-level register/memory access interfaces to simplify test case
writing.&nbsp; The test case writers would interface with abstract
system-level
data structures instead of low-level bits and bytes. <o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l2 level1 lfo2;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Automated configuration of complex memory architectures (FCRAM,
QDRRAM). <o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-tab-count:1'>
</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-tab-count:1'> </span><span
class=GramE>Also
worked as a general resource for <span class=SpellE>netlist</span> bring-up
and
test case debugging.</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>AUG99-FEB01 <span style='mso-tab-count:1'> </span><b
style='mso-bidi-font-weight:normal'>Analog Devices/Intel Joint Development
Project</b>, <st1lace w:st="on"><st1:City w:st="on">Austin</st1:City>,
<st1:State
w:st="on">Texas</st1:State></st1lace>.</span></span><span
style='font-size:
11.0pt;mso-bidi-font-size:10.0pt'>&nbsp; <span class=GramE>Responsible for
the
design and implementation of a simulation test bench for a new DSP core
being
developed jointly by ADI and Intel.</span>&nbsp; The test bench was
implemented
in Verilog (XL/VCS/NCVLOG).&nbsp;Some highlights of the test bench
include:<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Ability to load program code into L2-memory and instruction-cache
memory.<o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Ability to load program data into L2-memory and data-cache
memory.<o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Integration of an architectural reference model for the DSP core
into
the test bench. <o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Automated checking of register value changes using data from the
reference model. <o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Implementation of the entire 4GB L2 memory space using a sparse
memory
model. <o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Automated checking of program counter changes due to interrupts and
exceptions. <o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Very fast instruction execution (approximately 350 <span
class=GramE>instruction</span>
per second using compiled simulation). <o></o></span></p>

<p class=Experience style='margin-left:125.25pt;text-indent:-.25in;mso-list:
l0 level1 lfo1;tab-stops:89.25pt list 125.25pt'><![if !supportLists]><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:Symbol;
mso-fareast-font-family:Symbol;mso-bidi-font-family:Symbol'><span
style='mso-list:Ignore'><span style='font:7.0pt "Times New
Roman"'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp;
</span></span></span><![endif]><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Scripting language to control core inputs and to test core outputs
(resets, clocks, interrupts, exceptions, configuration pins, etc.).
<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-tab-count:1'>
</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-tab-count:1'> </span><span
class=GramE>Also
worked on a chip being developed solely by ADI using the DSP
core.</span>&nbsp;
This chip included the DSP core, a bridge from the core to several Amba
buses
(high and low speed), L2-memory, SDRAM controller, SRAM controller and
various
on-chip Amba bus peripherals (UART, SPORT, SPI, DMA engines, etc.).&nbsp; My
work involved real-time troubleshooting of the test bench and <span
class=SpellE>netlist</span> to enable test case writing to
continue.</span></p>

<p class=DefaultText><o>&nbsp;</o></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>MAR99-AUG99<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Compaq</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>,
<st1lace w:st="on"><st1:City w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span><span class=GramE>Responsible for the
block-level verification of a <b
style='mso-bidi-font-weight:normal'>PCI-X</b> <span
class=SpellE>megacell</span>.</span><span style='mso-spacerun:yes'>
</span>The
<span class=SpellE>megacell</span> converted <b style='mso-bidi-font-weight:
normal'>PCI-X</b> transactions to and from a proprietary on-chip interface
bus.<span style='mso-spacerun:yes'> </span>Developed test plans, coded a
random <b style='mso-bidi-font-weight:normal'>PCI-X</b> transaction
generator
for stress testing the <span class=SpellE>megacell</span> (using <b
style='mso-bidi-font-weight:normal'>Verilog-XL</b>), implemented test cases,
and helped supervise a group of co-op students at Texas <span
class=GramE>A&amp;M</span>
also working on the project.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Nov97-MAR99<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>AMD</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>,
<st1lace w:st="on"><st1:City w:st="on">Austin</st1:City>, <st1:State
w:st="on">Texas</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Responsible for the system-level
verification
of a system-on-a-chip consisting of an x86 microprocessor core, PCI host
bridge, SDRAM controller, ROM controller and various PC/AT compatible
devices
(8237 DMA, <span class=SpellE>UARTs</span>, RTC, PIC, etc.).<span
style='mso-spacerun:yes'> </span>The system test bench environment was
constructed using <span class=SpellE><b
style='mso-bidi-font-weight:normal'>Verisitys</b></span><b
style='mso-bidi-font-weight:normal'>'</b> e-language based verification tool
(<b
style='mso-bidi-font-weight:normal'>Specman</b>) integrated with <b
style='mso-bidi-font-weight:normal'>Verilog-XL</b> based bus function models
(PCI bus, x86 bus, SDRAM devices, ROM devices, etc.)</span><span
style='mso-spacerun:yes'> </span></p>

<p class=Experience><o>&nbsp;</o></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Nov96-Oct97<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>IBM</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>,
Microelectronics Division, <st1lace w:st="on"><st1:City w:st="on">Research
Triangle Park</st1:City>, <st1:State w:st="on">North
Carolina</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Responsible for the system-level
verification
of <span class=GramE>a</span> 1100K gate set-top-box ASIC.<span
style='mso-spacerun:yes'> </span>Developed bus functional models for
several
internal interconnect buses using <b
style='mso-bidi-font-weight:normal'>C++</b>.<span
style='mso-spacerun:yes'> </span>These models would interface to <span
class=SpellE>SpeedSims</span>' cycle-based simulator through the standard
PLI
interface. Developed and implemented test suites to verify the connectivity
of
the microprocessor core, cross-bar switch, MPEG-2 video and audio decoders,
DRAM, SRAM, SDRAM and other off-chip interfaces.<o></o></span></p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'><o>&nbsp;</o></span></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Jun 95-Nov 96<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Cisco Systems, </span></b><st1lace w:st="on"><st1:City
w:st="on"><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>Research Triangle
Park</span></st1:City><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>, <st1:State
w:st="on">North
Carolina</st1:State></span></st1lace><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>.</span></span><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'><span style='mso-spacerun:yes'> </span><span
class=GramE>Responsible for the system-level verification of the <b
style='mso-bidi-font-weight:normal'>Cisco 7200</b> series
router.</span><span
style='mso-spacerun:yes'> </span><span class=GramE>Developed verification
tools and turnkey regression test suites for three high-density printed
circuit
cards.</span><span style='mso-spacerun:yes'> </span>Verification was done
using the Cadence Verilog-XL simulator, <span class=SpellE>Synopsys</span>
<span
class=SpellE>SmartModels</span> and hardware models.<span
style='mso-spacerun:yes'> </span>System-level regression test suite was
written primarily in <span class=SpellE>Synopsys</span> PCL code.<span
style='mso-spacerun:yes'> </span>A Verilog behavioral model was created to
simulate the bus activity generated by various port adapter cards which plug
into
the router chassis via a PCI bus interface.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-tab-count:1'> </span><span
class=GramE>Also
developed a chip-level test bench for an ASIC that bridges token-ring frames
from a proprietary switching bus to a PCI bus.</span><span
style='mso-spacerun:yes'> </span>The test bench was developed using <b
style='mso-bidi-font-weight:normal'>Specman</b> (a next-generation
verification
tool from <span class=SpellE>Verisity</span>).<span
style='mso-spacerun:yes'>
</span>This tool was used to automatically generate token-ring frame
stimulus
and verify that the frame data was passed correctly through the chip based
on
the destination address, <st1lace w:st="on">RIF</st1lace>, SNAP and DSAP
fields.<o></o></span></p>

<p class=Experience><o>&nbsp;</o></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Feb94-Jun95<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Alcatel Network Systems</span></b><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>, <st1lace w:st="on"><st1:City
w:st="on">Raleigh</st1:City>,
<st1:State w:st="on">North
Carolina</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'> Developed drivers and
monitors (<b style='mso-bidi-font-weight:normal'>Verilog-XL</b>) to generate
and analyze STS-1, STS-3 and STS-12 stimulus patterns for an ASIC chipset
being
used in <span class=SpellE>Alcatels</span>' next generation SONET switches.
These drivers/monitors were integrated into a user-friendly test bench to
expedite system- level verification of the chipset.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience style='tab-stops:1.25in 1.5in 2.0in 2.5in 3.0in 3.5in
4.0in 4.5in 5.0in 5.5in 6.0in'><span
class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;text-transform:
uppercase'>Feb92-Feb94<span style='mso-tab-count:1'> </span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>IBM</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>,
Network Systems, <st1lace w:st="on"><st1:City w:st="on">Research Triangle
Park</st1:City>, <st1:State w:st="on">North
Carolina</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'> <span
class=GramE>Developed
behavioral models (<b style='mso-bidi-font-weight:normal'>Verilog-XL</b>) to
simulate the system-level environment of a full motion video co-processor
for
an IBM-PC graphics adapter card.</span> <span class=GramE>Responsible for
the
implementation of full chip simulation scenarios to test capabilities of the
co-processor which included scaling, cropping, dithering and YUV-RGB
conversion.</span><span style='mso-spacerun:yes'> </span>Behavioral models
generated
for system level functions included <span class=SpellE>VRAMs</span>, NTSC
and
compressed video data sources, host computer data source, memory bus
arbitration module and assorted analysis modules to track data flow inside
and
outside of the chip.<o></o></span></p>

<p class=DefaultText><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Times New Roman"'><o>&nbsp;</o></span></p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Nov88-Feb92<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Honeywell</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>, Commercial Flight Systems, <st1lace w:st="on"><st1:City
w:st="on">Phoenix</st1:City>,
<st1:State w:st="on">Arizona</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Designed, coded and tested software to
perform branch and code coverage analysis on an electronic flight
instrumentation system for the MD-11 commercial aircraft.<span
style='mso-spacerun:yes'> </span>This package consisted of: a pre-processor
<b
style='mso-bidi-font-weight:normal'>(VAX C)</b> to determine the possible
branches taken by the</span><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;font-family:"Arial MT"'> f</span><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>light software; a mid-processor <b
style='mso-bidi-font-weight:
normal'>(80386 Assembler)</b> to record the actual branches taken; a
post-processor <b style='mso-bidi-font-weight:normal'>(VAX C)</b> to compare
the possible with the actual branches and produce a coverage report
detailing
any unexecuted code or branches.<span style='mso-spacerun:yes'>
</span>Also,
developed software to provide <span class=SpellE>symbology</span> <span
class=GramE>for 80386 emulation on an HP9000 workstation</span>.<span
style='mso-spacerun:yes'> </span><span class=GramE>Also, developed software
to
facilitate functional testing of the flight
software.</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Arial MT"'><span style='mso-spacerun:yes'> </span><span
style='mso-tab-count:1'> </span></span><span
class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>Developed
a unique testing tool which allowed component integration-level tests to be
generated automatically from individual component-level tests resulting in a
dramatic reduction in man-hours required to certify the flight
software.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'> <o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-tab-count:1'> </span><span
class=GramE>Developed
a code-scanning compiler to verify the integrity of manually entered
data-dictionary information with procedure/variable references from the
source
code.</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'>Feb88-Aug88<span style='mso-tab-count:1'>
</span></span><st1:City
w:st="on"><b style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>Hamilton</span></b></st1:City><b
style='mso-bidi-font-weight:
normal'><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>
Standard</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>, <st1:City
w:st="on">Windsor</st1:City>
Locks, <st1:State w:st="on"><st1lace
w:st="on">Connecticut</st1lace></st1:State>.<span
style='mso-spacerun:yes'> </span>Designed, coded and tested software to
perform diagnostic testing on Full Authority Digital Engine Controls <b
style='mso-bidi-font-weight:normal'>(FADEC)</b> for large military jet
engines.<span style='mso-spacerun:yes'> </span>Software was written in
Pascal
for an HP9000.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Oct87-Feb88<span style='mso-tab-count:1'> </span><b
style='mso-bidi-font-weight:normal'>AT&amp;T Information Systems</b>,
<st1lace
w:st="on"><st1:City w:st="on">Denver</st1:City> <st1:State
w:st="on">Colorado</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'> Designed, coded and
tested
software to perform diagnostic testing on <b
style='mso-bidi-font-weight:normal'>ISDN
BRI</b> compatible terminals for the System 85 PBX.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Oct86-Oct87<span style='mso-tab-count:1'>
</span></span><span
class=SpellE><b style='mso-bidi-font-weight:normal'><span style='font-size:
11.0pt;mso-bidi-font-size:10.0pt'>Simmonds</span></b></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'> Precision</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>, <st1lace w:st="on"><st1:City w:st="on">Vergennes</st1:City>,
<st1:State
w:st="on">Vermont</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Designed, coded and tested software to
perform diagnostic testing on a fuel measurement and management system for
military aircraft.<span style='mso-spacerun:yes'> </span>This package
consisted of software running in the flight computer <b
style='mso-bidi-font-weight:
normal'>(MIL-STD-1750A or Fairchild 9450)</b> to perform functional testing
of
the hardware and software running on an IBM-PC <b
style='mso-bidi-font-weight:
normal'>(Microsoft C &amp; 8088 Assembler)</b> to control test execution and
error logging.<span style='mso-spacerun:yes'> </span>Challenges of this
assignment: a wide variety of communications interfaces <b
style='mso-bidi-font-weight:
normal'>(RS-232, IEEE 488, MIL-STD-1553)</b>; customized interrupt handlers
(UART, keyboard, timer); a wide variety of test equipment (HP6032A Power
Supply, LORAL SBA 100A, Control Systems Research MICRISTAR).<span
style='mso-spacerun:yes'> </span>Extensive documentation <b
style='mso-bidi-font-weight:
normal'>(MIL-STD-2167A)</b> was produced to satisfy the standards and
procedures of military contracts.<span style='mso-spacerun:yes'>
</span><span
class=GramE>Also, developed a Software Source Control System to help
maintain
customized releases of this package.</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'>Feb86-May86<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>General Electric, Co.</span></b><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>, <st1lace w:st="on"><st1:City
w:st="on">Somersworth</st1:City>,
<st1:State w:st="on">New Hampshire</st1:State></st1lace>.<span
style='mso-spacerun:yes'> </span>Made bug fixes/enhancements to EPROM
burning
software <b style='mso-bidi-font-weight:normal'>(FORTRAN 77)</b> used by GE
to
program their line of demand recording meters.<span
style='mso-spacerun:yes'>
</span>These enhancements included the ability to handle 256K <span
class=SpellE>EPROMs</span>, validation testing features and changing file
allocation from static to dynamic.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Feb85-Feb86<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Versatile Systems, Inc.</span></b><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>, <st1lace w:st="on"><st1:City
w:st="on">Belmont</st1:City>,
<st1:State w:st="on">California</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Designed, coded and tested software to
translate the database of one PC-based architectural drawing program to
another.<span style='mso-spacerun:yes'> </span><span class=GramE>Also,
developed a customized PILOT language
interpreter.</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'>Mar82-Feb85<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>VLSI Technology, Inc.</span></b><span style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>, <st1lace w:st="on"><st1:City w:st="on">San
Jose</st1:City>,
<st1:State w:st="on">California</st1:State></st1lace>.<span
style='mso-spacerun:yes'> </span><span class=GramE>Major contributor to the
<u>cell
compiler</u> project.</span><span style='mso-spacerun:yes'> </span>This is
a
library of customized hardware components</span><span
style='font-size:11.0pt;
mso-bidi-font-size:10.0pt;font-family:"Arial MT"'> </span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>generated by a collection
of
software elements called <u>cell compilers</u>.<span
style='mso-spacerun:yes'>
</span>These cells, by allowing a logic designer to create flexible building
blocks (i.e., registers, counters, <span class=SpellE>ALUs</span>), can
significantly reduce the time required to develop an ASIC.<span
style='mso-spacerun:yes'> </span>Consultant for several custom chip
projects:<span style='mso-spacerun:yes'> </span>Macintosh Computer for
Apple,
Atari home video game, Cable TV descrambler, Display Controller for a
portable
PC.<span style='mso-spacerun:yes'> </span>These projects encompassed all
aspects of VLSI chip design from schematic entry/logic simulation to cell
layout/chip composition.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Jun81-Mar82<span style='mso-tab-count:1'>
</span></span><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>Hewlett Packard</span></b><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'>, Disc Memory Division, <st1lace w:st="on"><st1:City
w:st="on">Boise</st1:City>,
<st1:State w:st="on">Idaho</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Designed, coded and tested software to
automatically generate <span class=SpellE>PLAs</span> for VLSI chips.<span
style='mso-spacerun:yes'> </span>This package consisted of: a compiler to
convert a high-level language description of the finite state machine
behavior
to truth tables; a logic <span class=SpellE>minimizer</span> to reduce the
truth tables; a PLA generator to convert the truth tables to mask
geometry.<o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span class=GramE><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt;text-transform:uppercase'>Sep73-Jun75<span style='mso-tab-count:1'>
</span></span><st1laceName
w:st="on"><b style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>South</span></b></st1laceName><b
style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt;mso-bidi-font-size:
10.0pt'> <st1laceName w:st="on">Burlington</st1laceName> <st1laceType
w:st="on">High School</st1laceType></span></b><span
style='font-size:11.0pt;
mso-bidi-font-size:10.0pt'>, <st1lace w:st="on"><st1:City w:st="on">South
Burlington</st1:City>, <st1:State
w:st="on">Vermont</st1:State></st1lace>.</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>Designed, coded and tested software to
perform class scheduling, produce class lists and to maintain attendance
records
for the school.<o></o></span></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'><o>&nbsp;</o></span></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'>EDUCATION</span></p>

<p class=DefaultText><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Arial MT"'><o>&nbsp;</o></span></p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'>June 1981<span style='mso-tab-count:1'>
</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>Master of Science in
Electrical Engineering program, <st1laceName
w:st="on">Dartmouth</st1laceName>
<st1laceType w:st="on">College</st1laceType>, Thayer School of
Engineering,
Hanover, <st1lace w:st="on"><st1:State w:st="on"><span
class=GramE>New</span>
Hampshire</st1:State></st1lace>.<span style='mso-spacerun:yes'>
</span><span
class=GramE>One year credit toward degree.</span><o></o></span></p>

<p class=Experience><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience><span style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'>June 1980<span style='mso-tab-count:1'>
</span></span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'>Bachelor of Science in
Computer Science with a minor in electrical engineering, Michigan State
University, East Lansing, Michigan.<span style='mso-spacerun:yes'>
</span><span
class=GramE>Graduated cum laude.</span><o></o></span></p>

<p class=Experience><o>&nbsp;</o></p>

<p class=Experience><span class=GramE><span
style='font-size:10.0pt;text-transform:
uppercase'>PATENTS</span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
text-transform:uppercase'><span style='mso-tab-count:1'>
</span></span><st1:country-region
w:st="on"><st1lace w:st="on"><b style='mso-bidi-font-weight:normal'><span
style='font-size:11.0pt'>United
States</span></b></st1lace></st1:country-region><b
style='mso-bidi-font-weight:normal'><span style='font-size:11.0pt'> Patent
#6,052,745</span></b><span
style='font-size:11.0pt'>, System for asserting burst termination signal and
burst
complete signal one cycle prior to and during last cycle in fixed length
burst
transfers.</span></span><span style='font-size:11.0pt'> </span><span
style='font-size:11.0pt;font-family:"Arial MT"'><o></o></span></p>

<p class=DefaultText><span
style='font-size:10.0pt;font-family:Rockwell'>PUBLICATIONS</span></p>

<p class=DefaultText><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Times New Roman"'><o>&nbsp;</o></span></p>

<p class=Experience style='tab-stops:.5in 1.25in 1.5in 2.0in 2.5in 3.0in
3.5in 4.0in 4.5in 5.0in 5.5in 6.0in'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>[1]<span style='mso-tab-count:2'>
</span><b
style='mso-bidi-font-weight:normal'>Cell Compilers vs. Standard Cell
Design</b>,
Custom Integrated Circuits Conference, <st1lace w:st="on"><st1:City
w:st="on">Rochester</st1:City>,
<st1:State w:st="on">NY</st1:State></st1lace>,
1984.<o></o></span></p>

<p class=Experience style='tab-stops:.5in 1.25in 1.5in 2.0in 2.5in 3.0in
3.5in 4.0in 4.5in 5.0in 5.5in 6.0in'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience style='tab-stops:.5in 1.25in 1.5in 2.0in 2.5in 3.0in
3.5in 4.0in 4.5in 5.0in 5.5in 6.0in'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>[2]<span style='mso-tab-count:2'>
</span><b
style='mso-bidi-font-weight:normal'>Cell Layout Compilers Simplify Custom IC
Design</b>, EDN, <span class=GramE>September</span> 15,
1983.<o></o></span></p>

<p class=Experience style='tab-stops:.5in 1.25in 1.5in 2.0in 2.5in 3.0in
3.5in 4.0in 4.5in 5.0in 5.5in 6.0in'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><o>&nbsp;</o></span><
/p>

<p class=Experience style='tab-stops:.5in 1.25in 1.5in 2.0in 2.5in 3.0in
3.5in 4.0in 4.5in 5.0in 5.5in 6.0in'><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt'><span
style='mso-spacerun:yes'> </span>[3]<span style='mso-tab-count:2'>
</span><b
style='mso-bidi-font-weight:normal'>Automatic PLA Generation</b>, Hewlett
Packard VLSI Conference, <st1lace w:st="on"><st1:City w:st="on"><span
class=SpellE>Corvalis</span></st1:City>, <st1:State
w:st="on">Oregon</st1:State></st1lace>,
1981.</span><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;font-family:
"Arial MT"'><o></o></span></p>

<p class=DefaultText><span
style='font-size:11.0pt;mso-bidi-font-size:10.0pt;
font-family:"Times New Roman"'><o>&nbsp;</o></span></p>

</div>

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Igmar Palsenberg
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      09-25-2003


You seriously anyone would read something in some vague MS XML format ?
I doubt it...




Igmar

 
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Andy Peters
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      09-26-2003
Igmar Palsenberg <(E-Mail Removed)> wrote in message news:<3f732c73$0$58710$(E-Mail Removed)4all.nl>...
> You seriously anyone would read something in some vague MS XML format ?
> I doubt it...


This part was funny:

<o:LastAuthor>Sam Gamgee</o:LastAuthor>

Yep, he's hired. Starts tomorrow.

Thank you, drive through.

-a
 
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