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how to implement gated clock and gated partial circuit in VHDL?

 
 
walala
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      09-20-2003
Dear all,

I heard about a quite effective low power technique buzzword: "gated clock"
and/or "gated" sub-circuit for long. But I don't know how to implement this
in VHDL? Can anybody point me to some resources which have
easy-to-understand and practical samples or template that I can follow...?

Thanks a lot,

-Walala


 
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Roadie Roger
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      09-22-2003
"walala" <(E-Mail Removed)> wrote in message news:<bkhrbb$fhn$(E-Mail Removed)>...
> Dear all,
>
> I heard about a quite effective low power technique buzzword: "gated clock"
> and/or "gated" sub-circuit for long. But I don't know how to implement this
> in VHDL? Can anybody point me to some resources which have
> easy-to-understand and practical samples or template that I can follow...?
>
> Thanks a lot,
>
> -Walala


Actually gating clocks is relatively evil. Having a gated clock that
transitions less often does save power. Every signal edge is a power
waster in the face of capacitance. Gated clocks create other
problems. Your clocks are no longer exactly lined up. Many chips
have a global clock that goes everywhere. Breaking it into pieces
isn't a good thing. You want to enable data rather than gate clocks.
Call the Enable 'E'. This looks something like:

If CLK'event and CLK = '1' then
Q <= (not(E) and Q) or (D and Q) or (D and E);
end if;

I realize this doesn't tell you how to gate clocks. I'm not gonna
tell you, because I can't tell you how to fix the problems it creates.

Happy Designing,
Roadie Roger
<http://home.earthlink.net/~roadieroger/index.htm>
 
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Robert Reutemann
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      09-23-2003
>>I heard about a quite effective low power technique buzzword: "gated clock"
>>and/or "gated" sub-circuit for long. But I don't know how to implement this
>>in VHDL? Can anybody point me to some resources which have
>>easy-to-understand and practical samples or template that I can follow...?

>
> Actually gating clocks is relatively evil. Having a gated clock that
> transitions less often does save power. Every signal edge is a power
> waster in the face of capacitance. Gated clocks create other
> problems. Your clocks are no longer exactly lined up. Many chips
> have a global clock that goes everywhere. Breaking it into pieces
> isn't a good thing. You want to enable data rather than gate clocks.
> Call the Enable 'E'. This looks something like:
>
> If CLK'event and CLK = '1' then
> Q <= (not(E) and Q) or (D and Q) or (D and E);
> end if;
>
> I realize this doesn't tell you how to gate clocks. I'm not gonna
> tell you, because I can't tell you how to fix the problems it creates.
>
> Happy Designing,
> Roadie Roger


Depends on your target technology. The above may hold for FPGA's,
but for standard-cell based ASIC technologies, gated clocks are
an elegant (in my opinion) and clean methodology for low-power
design.

In this case, you will most likely be using a clock tree generator
anyway, and all of the clock tree generators I know easily handle
clock gates. They will automatically align the clocks AFTER any
possible gates, i.e. at the leaf nodes (clock inputs of registers).
In this case, generating a low-skew clock tree is far easier for
gated clocks than for derived clocks (i.e. divided clocks).

Modern synthesis tools also can insert clock gates automatically
by replacing register enables (as shown in the post above) by
gated clocks. This can be handy, but it has the drawback of
reducing your control over clock gates (names, hierarchy).

Inserting clock gates in a VHDL design is easy. Just decide what
gating style you want/need (and/or based, with/without latch, with
test bypass, observability, ...).

My choice is to then explicitly instantiate a clock gating
element where needed. This has the disadvantage of requiring one
to "route" different clock signals through the design, but
it gives you full control over clock gating elements for use
in later stages of the design (clock tree generation, physical
optimization, ...).

Information about "clean" clock gating can be found in books
or also in synthesis tool manuals (where automatic clock
gate insertion is described). Probably you'll also find
resources on the web.

Robert

 
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Roadie Roger
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Posts: n/a
 
      09-23-2003
Robert Reutemann <(E-Mail Removed)> wrote in message news:<3f703489$(E-Mail Removed)>...
> >>I heard about a quite effective low power technique buzzword: "gated clock"
> >>and/or "gated" sub-circuit for long. But I don't know how to implement this
> >>in VHDL? Can anybody point me to some resources which have
> >>easy-to-understand and practical samples or template that I can follow...?

> >
> > Actually gating clocks is relatively evil. Having a gated clock that
> > transitions less often does save power. Every signal edge is a power
> > waster in the face of capacitance. Gated clocks create other
> > problems. Your clocks are no longer exactly lined up. Many chips
> > have a global clock that goes everywhere. Breaking it into pieces
> > isn't a good thing. You want to enable data rather than gate clocks.
> > Call the Enable 'E'. This looks something like:
> >
> > If CLK'event and CLK = '1' then
> > Q <= (not(E) and Q) or (D and Q) or (D and E);
> > end if;
> >
> > I realize this doesn't tell you how to gate clocks. I'm not gonna
> > tell you, because I can't tell you how to fix the problems it creates.
> >
> > Happy Designing,
> > Roadie Roger

>
> Depends on your target technology. The above may hold for FPGA's,
> but for standard-cell based ASIC technologies, gated clocks are
> an elegant (in my opinion) and clean methodology for low-power
> design.
>
> In this case, you will most likely be using a clock tree generator
> anyway, and all of the clock tree generators I know easily handle
> clock gates. They will automatically align the clocks AFTER any
> possible gates, i.e. at the leaf nodes (clock inputs of registers).

In that case, I withdraw my objection. Go for it
 
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