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Hello again,

I have an array of 16 10 bit coefficients, and I would like to store
these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
Altera devices by selecting various options say on Quartus, or can I
switch on any synthesis switches or do I have to change my VHDL. Any ideas
as always is greatly appreciated.

Thanks
Bob

Bob,
If your coefficients are constants and you use those
constants in your design, there is nothing to store.
During synthesis the constants reduce to pull-up and
pull-down and then further optimize away portions of
the circuit.

If your coefficients are not constants, then they would
need to be stored in either a register or a RAM.
If use a register coding style for your coefficients, then
they will be realized in a LUT.

If you need further help, you may wish to either further
describe your problem or post your code.

Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Bob wrote:

> Hello again,
>
> I have an array of 16 10 bit coefficients, and I would like to store
> these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
> Altera devices by selecting various options say on Quartus, or can I
> switch on any synthesis switches or do I have to change my VHDL. Any ideas
> as always is greatly appreciated.
>
> Thanks
> Bob